DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/17/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
4. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Drawings
5. The drawings are objected to because:
Fig. 7 missing label for “NOT” gate generating delayed clock signal CLK at node N6X.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
6. Claims 1 is objected to because of the following informalities:
Claim 1 recites lines 3 and 6 recites “receive first input, a magnitude of the first input derived from” and “receive second input indicating a magnitude of first output current”, respectively. However, it appears that it should recite “receive a first input, a magnitude of the first input derived from” and “receive a second input indicating a magnitude of the first output current”, respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claim(s) 1 - 13, 15 - 19 and 22 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US Pub. No. 2020/0381998 A1; (hereinafter McKenzie).
Regarding claim 1, McKenzie [e.g., Figs. 1 - 4B] discloses an apparatus [e.g., -- refer to Fig. 1 for power converter 120 --] comprising: a power converter controller [e.g., Smart Power Stage (SPS1)] operative to: receive first input [e.g., -- refer to Fig. 3A for architecture of SPS --, SPSi receives V1 (combination of VREFIN and voltage source (310)) via Delay Modulation Engine (DME) 315], a magnitude of the first input derived from combined output current supplied from multiple power converters to a load [e.g., p. 0024 recites “In some embodiments, the voltage source 310 may be a signal generated by an SPS1 that represents a scaled version of the output current Iouti (e.g., the current through inductor 140).”]; receive second input [e.g., current monitor output signal (IMON1)] indicating a magnitude of first output current supplied from a first power converter of the multiple power converters to the load [e.g., IMON1 indicates an average current supplied by SPS1, p. 0023 recites “… each current monitor output signal (e.g., IMON1, IMON2, IMON3, IMON4) generated by each smart power stage may substantially represent a function (e.g., an average) current monitor output signal, and a total current monitor output (IMON) of the SPS system 135 is reported to the PWM controller 125.”], the combined output current including the first output current [e.g., IMON1 is part of IMON, p. 0024 recites “The IMONi is part of the total output (e.g., IMON) that is returned to the PWM controller 125. The IMONi contains the SPSi MOSFET load current information that may be used for load telemetry and control.”]; and based on a comparison of the second input to the first input [e.g., -- refer to Fig 3B for an architecture of an exemplary delay modulation engine (DME) of the SPS -- comparison done by amplifier (350) and resistor Rs (340)], adjusting a leading edge and a trailing edge of a first pulse width modulation control signal [e.g., p.0034 recites “The leading edge and/or the trailing edge of PWMi may be adjusted in response to the voltage difference of two electrical terminals of a resistor (e.g., resistor Rs 340). More specifically, the leading edge of PWMi may be delayed to shorten pulse width, and therefore, a phase current may be decreased. The trailing edge of PWMi may be delayed to lengthen pulse width and therefore, a phase current may be increased. Thus, phase current IMONi of each SPS in an SPS system may be dynamically adjusted.”].
Regarding claim 2, McKenzie [e.g., Figs. 1 - 4B] discloses wherein the first pulse width modulation control signal [e.g., PWM1] is operative to control a magnitude of the first output current supplied from the first power converter [e.g., MOSFET Driver 325 controls with PWMi, p.0019 recites “… the PWM controller 125 generates one or more pulse width modulation (PWM) signals (e.g., PWM1 signal 1301, PWM2 signal 1302, . . . , PWMn signal 130n) with commanded duty cycle at the frequency of fsw.”].
Regarding claim 3, McKenzie [e.g., Figs. 1 - 4B] discloses wherein the adjusted leading edge and the trailing edge of the first pulse width modulation control signal [e.g., adjusted leading and trailing edge of PWM1] is operative to set the magnitude of the first output current supplied from the first power converter to be substantially equal to the magnitude of the first input [e.g., can set magnitude of output current supplied by SPS1 to match signal generated by Iout, p.0026 recites “the delay modulation engine may be configured to add or remove delay to the leading or trailing edges of the PWM signal from the PWM controller 125 in order to regulate the corresponding stage current to substantially match, for example, an average value of the output current (e.g., IMON/N).”].
Regarding claim 4, McKenzie [e.g., Figs. 1 - 4B] discloses wherein a magnitude of the first input e.g., -- refer to Fig. 3A for architecture of SPS --, magnitude of V1(combination of VREFIN and voltage source (310))] indicates an average magnitude of current supplied from the multiple power converters to the load [e.g., p. 0024 recites “In some embodiments, the voltage source 310 may be a signal generated by an SPS1 that represents a scaled version of the output current Iouti (e.g., the current through inductor 140).”].
Regarding claim 5, McKenzie [e.g., Figs. 1 - 4B] discloses wherein the power converter controller is further operative to: receive the first pulse width modulation control signal from a pulse width modulation signal generator controlling operation of the multiple power converters [e.g., -- refer to Fig. 2 --, PWM1 generated by PWM Controller 125, p.0019 recites “The PWM controller may, in response to the current monitor output signals, adjust the duty cycle of the stage power output signals PWMi′ in order, for example, to adjust a voltage level for Vout.”]; derive a second pulse width modulation control signal from the received first pulse width modulation control signal the end the adjusted leading edge and the trailing edge leading-edge is a trailing edge [e.g., -- refer to Fig. 3A -- , derives PWMi’ via Delay Modulation Engine (DME) 315]; and output the second pulse width modulation control signal to the first power converter [e.g., output PWMi’ (320) to MOSFET Driver 325].
Regarding claim 6, McKenzie [e.g., Figs. 1 - 4B] discloses wherein the first pulse width modulation control signal and the second pulse width modulation control signal are generated at a same frequency [e.g., p.0019 recites “In an illustrative example, the PWM controller 125 generates one or more pulse width modulation (PWM) signals (e.g., PWM1 signal 1301, PWM2 signal 1302, . . . , PWMn signal 130n) with commanded duty cycle at the frequency of fsw.”].
Regarding claim 7, McKenzie [e.g., Figs. 1 - 4B] discloses an apparatus [e.g., -- refer to Fig. 1 for power converter 120 --] comprising: a first power converter controller [e.g., Smart Power Stage (SPS1)] operative to: receive a first control signal from a current controller [e.g., receives PWM1 (130) generated by PWM Controller 125], the first control signal generated by the current controller to control delivery of output currents from multiple power converters to a load [e.g., p.0019 recites “In an illustrative example, the PWM controller 125 generates one or more pulse width modulation (PWM) signals (e.g., PWM1 signal 1301, PWM2 signal 1302, . . . , PWMn signal 130n) with commanded duty cycle at the frequency of fsw.”]; derive a second control signal from the received first control signal [e.g., -- refer to Fig. 3A --, derives PWMi’ (320) via Delay Modulation Engine (DME) 315], the second control signal operative to control a first power converter [e.g., PWMi’ (320) controls MOSFTER Driver 315]; and wherein the second control signal includes a leading edge followed by a trailing edge [e.g., PWMi’ (320) is the adjusted PWMi with corresponding leading and/or trailing edges, p. 0024 recites “The delay modulation engine 315 generates a duty cycle (e.g., pulse width) adjusted PWM signal 320 (e.g., PWMi′) in response to a received PWM signal (e.g., PWMi generated by the PWM controller 125),..”], the leading edge of the second control signal adjusted over time by the first power converter controller to balance magnitudes of the output currents from the multiple converters [e.g., p. 0034 recites “The leading edge and/or the trailing edge of PWMi may be adjusted in response to the voltage difference of two electrical terminals of a resistor (e.g., resistor Rs 340). More specifically, the leading edge of PWMi may be delayed to shorten pulse width, and therefore, a phase current may be decreased. The trailing edge of PWMi may be delayed to lengthen pulse width and therefore, a phase current may be increased. Thus, phase current IMONi of each SPS in an SPS system may be dynamically adjusted.”. Additionally, p. 0044 recites “Accordingly, all stages may independently, simultaneously, continuously and automatically seek to substantially regulate, in real time, their corresponding output currents based on a share of an average of the total output current, thus achieving continuous time current balance and sharing benefits.”].
Regarding claim 8, McKenzie [e.g., Figs. 1 - 4B] discloses wherein the leading edge of the second control signal [e.g., leading edge of PWMi’] is adjusted based on a difference between an average magnitude of the output currents [e.g., VREFIN] and a determined magnitude of the first output current [e.g., IMONi] outputted from the first power converter to the load [e.g., -- refer to Fig. 3B --, leading edge of PWMi’ adjusted based on difference between signal VREFIN and IMON performed by amplifier 350, p. 0033 recites “The error signal at the input of the amplifier 350 may be a function of a difference (e.g., amplitude and sign) between the average stage current amplitude and the average total current amplitude (e.g., IMON).”. It continues on p. 0034 recites “The leading edge and/or the trailing edge of PWMi may be adjusted in response to the voltage difference of two electrical terminals of a resistor (e.g., resistor Rs 340).”].
Regarding claim 9, McKenzie [e.g., Figs. 1 - 4B] discloses an apparatus [e.g., -- refer to Fig. 1 for power converter 120 --] comprising: a first power converter controller [e.g., Smart Power Stage (SPS1)] operative to: output a first output signal from the first power converter controller over a shared signal path to a current controller [e.g., -- refer to Fig. 2 for connections between the exemplary SPS system and a PWM controller in the power converter --, IMON1 via shared line for outputting IMON to PWM controller 125], the first output signal indicating a magnitude of first output current supplied by a first power converter phase to a load [e.g., IMON1 indicates an average current supplied by SPS1, p. 0023 recites “… each current monitor output signal (e.g., IMON1, IMON2, IMON3, IMON4) generated by each smart power stage may substantially represent a function (e.g., an average) current monitor output signal, and a total current monitor output (IMON) of the SPS system 135 is reported to the PWM controller 125.”], the shared signal path operative to receive a second output signal from a second power converter controller [e.g., shared line between PWM Controller 125 and SPS2 receives IMON2 via SPS2], the second output signal indicating a magnitude of second output current supplied by the second power converter to the load [e.g., IMON2 indicates an average current supplied by SPS2, p. 0023 recites “The total current monitor output (IMON) is a combination of IMON output signals from each of the SPSs in the SPS system 135.”]; receive a first control signal from the current controller [e.g., PWM1], the first control signal generated by the current controller based on the first output signal and the second output signal [e.g., PWM signals generated based on IMONi, p. 0020 recites “To complete a DC-DC system, the PWM controller 125 may also receive a composite of stage current monitor output signals (e.g., IMON1, IMON2, IMON3, IMON4) to adjust a duty cycle of the PWM signals that the PWM controller 125 supplies to each stage”]; and derive a second control signal from the received first control signal [e.g., -- refer to Fig. 3A --, derives PWMi’ (320) via Delay Modulation Engine (DME) 315], a pulse width of the second control signal being adjusted with respect to a pulse width of the first control signal [e.g., PWM1’ adjusted with respect to PWM1 by Delay Modulation Engine 315].
Regarding claim 10, McKenzie [e.g., Figs. 1 - 4B] discloses wherein the first power converter controller [e.g., SPS1] is further operative to derive the second control signal [e.g., PWMi’] based on a first delay value [e.g., -- refer to Fig. 4A - 4B for timing diagram --, leading edge delayed PWMi signal] and a second delay value [e.g., trailing edge delayed PWMi signal]; wherein a leading edge of the first control signal is delayed by the first delay value to produce a leading edge of the second control signal [e.g., delay applied to leading edge of PWM1 to generate updated leading edge PWM1’ (320)]; and wherein a trailing edge of the first control signal is delayed by the second delay value to produce a trailing edge of the second control signal [e.g., delay applied to trailing edge of PWM1 to generate updated trailing edge delayed PWM1’ signal (320), p. 0034 recites “FIG. 4A depicts timing diagrams of an incoming PWM signal and exemplary duty cycle adjusted PWM signals. In this depicted example, an incoming PWM signal is a positive pulse signal. As shown in FIG. 4A, pulse width (e.g., a function of duty cycle) of the incoming PWM signal (e.g., PWMi) generated by a controller (e.g., the PWM controller 125) may be adjusted (e.g., by the power stage control logic 315 of SPS). The leading edge and/or the trailing edge of PWMi may be adjusted in response to the voltage difference of two electrical terminals of a resistor (e.g., resistor Rs 340). More specifically, the leading edge of PWMi may be delayed to shorten pulse width, and therefore, a phase current may be decreased. The trailing edge of PWMi may be delayed to lengthen pulse width and therefore, a phase current may be increased. Thus, phase current IMONi of each SPS in an SPS system may be dynamically adjusted.”].
Regarding claim 11, McKenzie [e.g., Figs. 1 - 4B] discloses wherein the first power converter controller [e.g., SPS1] is further operative to: receive an input signal from the shared signal path [e.g., -- refer to Fig. 2 for connections between the exemplary SPS system and a PWM controller in the power converter --, IMON1 received by SPS1 via shared line (IMON line)], the received input signal indicating an average magnitude value based on the first output current supplied by the first power converter phase to the load and the second output current supplied by the second power converter phase to the load [e.g., indicates average magnitude of total output p. 0026 recites “…, the delay modulation engine may be configured to add or remove delay to the leading or trailing edges of the PWM signal from the PWM controller 125 in order to regulate the corresponding stage current to substantially match, for example, an average value of the output current (e.g., IMON/N). By causing each of the stages to autonomously and substantially track an average current across all phases, the overall system may advantageously maintain substantially balanced currents such that, for example, power dissipation, current, and/or voltage stresses may be substantially minimized, which may result in improved service life, and/or reduced ripple voltage in some examples..”]; receive a first current monitor signal indicating the magnitude of the first output current [e.g., receive IMON1 which indicates an average current supplied by SPS1, p. 0023 recites “… each current monitor output signal (e.g., IMON1, IMON2, IMON3, IMON4) generated by each smart power stage may substantially represent a function (e.g., an average) current monitor output signal, and a total current monitor output (IMON) of the SPS system 135 is reported to the PWM controller 125.”]; and produce the first delay value and the second delay value based on a comparison of: i) the received input signal indicating the average magnitude value, and ii) the first current monitor signal indicating the magnitude of the first output current [e.g., produce leading and trailing edge delays based on average output current of the power stage and/or average of the N output current, p. 0049 recites “…. Each power stage of the plurality of power stages includes a delay modulation engine that includes (1) a first input node coupled to receive a first signal representative of an output current signal of the corresponding power stage, (2) a second input node coupled to receive a second signal representative of an average of the N output currents, (3) a detection circuit coupled to the first input node and to the second input node and configured to determine a difference between the first signal and the second signal, and, (4) a processing circuit coupled to receive a signal representative of the difference from the detection circuit, and further configured to generate the respective output signal by applying a delay to an edge of the corresponding pulse width modulation signal.”].
Regarding claim 12, McKenzie [e.g., Figs. 1 - 4B] discloses wherein the first power converter controller is further operative to: adjust a magnitude of the first delay value and a magnitude of the second delay value [e.g., -- refer to Fig. 4A --, SPSi adjust magnitude of trailing edge and leading edge of PWMi (leading edge and trailing edge delayed PWMi signal)] such that the magnitude of the second pulse width is greater than the magnitude of the first pulse width in response to detecting [e.g., magnitude of trailing edge delayed PWMi signal greater than magnitude of Positive PWMi signal] a condition in which the magnitude of the first output current is less than the average magnitude value [e.g., p. 0034 recites “FIG. 4A depicts timing diagrams of an incoming PWM signal and exemplary duty cycle adjusted PWM signals. In this depicted example, an incoming PWM signal is a positive pulse signal. As shown in FIG. 4A, pulse width (e.g., a function of duty cycle) of the incoming PWM signal (e.g., PWMi) generated by a controller (e.g., the PWM controller 125) may be adjusted (e.g., by the power stage control logic 315 of SPS). The leading edge and/or the trailing edge of PWMi may be adjusted in response to the voltage difference of two electrical terminals of a resistor (e.g., resistor Rs 340). … The trailing edge of PWMi may be delayed to lengthen pulse width and therefore, a phase current may be increased. Thus, phase current IMONi of each SPS in an SPS system may be dynamically adjusted.”].
Regarding claim 13, McKenzie [e.g., Figs. 1 - 4B] discloses wherein the first power converter controller is further operative to: adjust a magnitude of the first delay value and a magnitude of the second delay value [e.g., -- refer to Fig. 4A --, SPSi adjust magnitude of trailing edge and leading edge of PWMi (delayed PWMi signal)] such that the magnitude of the second pulse width is less than the magnitude of the first pulse width [e.g., magnitude of leading edge delayed PWMi signal less than magnitude of Positive PWMi signal] in response to detecting a condition in which the magnitude of the first output current is less than the average magnitude value [e.g., p. 0034 recites “The leading edge and/or the trailing edge of PWMi may be adjusted in response to the voltage difference of two electrical terminals of a resistor (e.g., resistor Rs 340). More specifically, the leading edge of PWMi may be delayed to shorten pulse width, and therefore, a phase current may be decreased.”].
Regarding claim 15, McKenzie [e.g., Figs. 1 - 4B] discloses wherein the first control signal is a first pulse width modulation control signal [e.g., PWM1]; wherein the first power converter controller is operative to control the magnitude of the first output current based on the first pulse width modulation control signal received from the current controller [e.g., respective MOSFET Driver 325 controlled with respective PWMi, p.0019 recites “… the PWM controller 125 generates one or more pulse width modulation (PWM) signals (e.g., PWM1 signal 1301, PWM2 signal 1302, . . . , PWMn signal 130n) with commanded duty cycle at the frequency of fsw.”]; and wherein the second power converter controller [e.g., SPS2] is operative to control the magnitude of the second output current based on a second pulse width modulation control signal received from the current controller [e.g., respective MOSFET Driver 325 controlled with respective PWMi, p.0019 recites “… the PWM controller 125 generates one or more pulse width modulation (PWM) signals (e.g., PWM1 signal 1301, PWM2 signal 1302, . . . , PWMn signal 130n) with commanded duty cycle at the frequency of fsw.”].
Regarding claim 16, McKenzie [e.g., Figs. 1 - 4B] discloses wherein the first power converter controller is further operative to: generate a first error signal [e.g., -- refer to Fig. 3B --, first difference signal 365a via first comparator 360a] based on a difference between a target value associated with producing the magnitude of the first output current [e.g., voltage VA indicates current level of delivered output by SPSi, p. 0027 recites “When the difference between the reference voltage VREFIN and the amplified voltage (e.g., VA) is positive and exceeds the first predetermined dead zone, the first control signal 365a may imply that the current of SPSi is above an average current (e.g., IMONi>IMON/N).”] and a measured magnitude of the first output current supplied to the load [e.g., VREFIN, p.0024 recites “the voltage source 310 may be a signal generated by an SPS1 that represents a scaled version of the output current Iouti (e.g., the current through inductor 140)]; and generate a second error signal [e.g., 365b via second comparator 360b] based on a difference between the target value associated with producing the magnitude of the first output current [e.g., voltage VA indicates current level of delivered output by SPSi] and the measured magnitude of the first output current supplied to the load [e.g., VREFIN, p. 0028 recites “The second control signal 365b may imply that the current of SPSi is below the average current (e.g., IMONi<IMON/N). In some embodiments, the range of the first predetermined dead zone may be equal to the range of the second predetermined dead zone.” Additionally p. 0044 recites “In some implementations, a detection circuit in one of the stages (SPS) may determine a sign and/or magnitude of a difference between the stage phase current and an average of phase currents in all stages.”].
Regarding claim 17, McKenzie [e.g., Figs. 1 - 4B] discloses wherein the first power converter controller is further operative to: depending on a magnitude and polarity of the first error signal [e.g., magnitude and polarity of 365a, p. 0044 recites “In some implementations, a detection circuit in one of the stages (SPS) may determine a sign and/or magnitude of a difference between the stage phase current and an average of phase currents in all stages.”], adjust timing of a leading edge of the second control signal [e.g., adjust leading edge of PWMi’, p. 0030 recites “More specifically, when difference between the reference voltage VREFIN and the amplified voltage VA is larger than the first dead zone value, which means the SPSi may have too much current. Thus, the delay circuit 380 may delay the leading edge of PWMi. Thus, the pulse width of PWMi may be shortened to source less current.”]; and depending on a magnitude and polarity of the second error signal [e.g., magnitude and polarity of 365b, p. 0044 recites “In some implementations, a detection circuit in one of the stages (SPS) may determine a sign and/or magnitude of a difference between the stage phase current and an average of phase currents in all stages.”], adjust timing of a trailing edge of the second control signal [e.g., adjust trailing edge of PWMi’, p. 0031 recites “When the difference between the amplified voltage VA and the reference voltage VREFIN is larger than the second dead zone value, which means the SPSi may have too little current. The delay circuit 380 may delay the trailing edge of PWMi to increase the pulse width of PWMi to have more current.”].
Regarding claim 18, McKenzie [e.g., Figs. 1 - 4B] discloses wherein the first power converter controller is further operative to: control activation of high side switch circuitry in the first power converter via the second control signal [e.g., -- refer to Fig. 3A --, PWM1’ (320) control activation of high side switch 330], the controlled activation of the high side switch circuitry using the second control signal operative to substantially equalize the magnitude of the first output current and the second output current over time [e.g., p. 0025 recites “The MOSFET driver 325 switches a high side switch (e.g., transistor) 330 and a low side switch (e.g., transistor) 335 to create a regulated voltage across an inductor in the output circuit 140, for example. By using the delay modulation engine (DME), pulse width of a PWM signal may be locally and autonomously adjusted within each SPS to achieve substantially evenly distributed current sharing among all active phases of an SPS system.” Additionally, p.0044 recites “Accordingly, all stages may independently, simultaneously, continuously and automatically seek to substantially regulate, in real time, their corresponding output currents based on a share of an average of the total output current, thus achieving continuous time current balance and sharing benefits.”].
Regarding claim 19, McKenzie [e.g., Figs. 1 - 4B] discloses wherein derivation of the control signal from the received first control signal [e.g., derivation of PWMi’ (320) from PWMi] includes: selection of a first delay signal from a first tapped delay line to control a respective timing of a leading edge of the second control signal [e.g., signal 365a, Up/Down Counter 370 and Delay circuit 380, p. 0030 recites “The output of the up/down counter 370 is received by a delay circuit 380. The delay circuit 380 delays the leading edge or the trailing edge of PWM1 to adjust the pulse width of PWM1 in response to the output of the up/down counter 370 and PWM1. More specifically, when difference between the reference voltage VREFIN and the amplified voltage VA is larger than the first dead zone value, which means the SPSi may have too much current. Thus, the delay circuit 380 may delay the leading edge of PWMi. Thus, the pulse width of PWMi may be shortened to source less current.”. Additionally, p. 0042 recites “Although up/down counter was described with reference to FIG.3B, other implementations may employ other techniques to controllably adjust the delay to effect current balance among the phase currents. Some embodiments may implement a controlled delay using, for example, voltage sensitive varactors or switched capacitor network to form, for example, a programmable delay line. Some embodiments may implement an adjustable delay using a ramp/threshold comparison circuit, for example.”]; and selection of a second delay signal from a second tapped delay line to control a respective timing of a trailing edge of the second control signal [e.g., signal 365a, Up/Down Counter 370 and Delay circuit 380, p. 0031 recites “When the difference between the amplified voltage VA and the reference voltage VREFIN is larger than the second dead zone value, which means the SPSi may have too little current. The delay circuit 380 may delay the trailing edge of PWMi to increase the pulse width of PWMi to have more current.” Additionally, p. 0042 recites “Although up/down counter was described with reference to FIG.3B, other implementations may employ other techniques to controllably adjust the delay to effect current balance among the phase currents. Some embodiments may implement a controlled delay using, for example, voltage sensitive varactors or switched capacitor network to form, for example, a programmable delay line. Some embodiments may implement an adjustable delay using a ramp/threshold comparison circuit, for example.”].
Regarding claim 22, McKenzie [e.g., Figs. 1 - 4B] discloses wherein the first power converter controller is operative to: implement a first continuous delay element circuit [e.g., Processing circuit containing Up/Down Counter 370 and Delay Circuit 380 with comparator 360a] to convert the first control signal into the second control signal [e.g., converts PWMi into PWMi’ (320)], the first continuous delay element circuit operative to control timing of a leading edge of the second control signal [e.g., signal 365a, Up/Down Counter 370 and Delay circuit 380, p. 0030 recites “The output of the up/down counter 370 is received by a delay circuit 380. The delay circuit 380 delays the leading edge or the trailing edge of PWM1 to adjust the pulse width of PWM1 in response to the output of the up/down counter 370 and PWM1. More specifically, when difference between the reference voltage VREFIN and the amplified voltage VA is larger than the first dead zone value, which means the SPSi may have too much current. Thus, the delay circuit 380 may delay the leading edge of PWMi. Thus, the pulse width of PWMi may be shortened to source less current.”]; and implement a second continuous delay element circuit to convert the first control signal into the second control signal [e.g., Processing circuit containing Up/Down Counter 370 and Delay Circuit 380 with comparator 360b], the second current continuous delay element circuit operative to control timing of a trailing edge of the second control signal [e.g., signal 365b, Up/Down Counter 370 and Delay circuit 380, p. 0031 recites “When the difference between the amplified voltage VA and the reference voltage VREFIN is larger than the second dead zone value, which means the SPSi may have too little current. The delay circuit 380 may delay the trailing edge of PWMi to increase the pulse width of PWMi to have more current.” Additionally, p. 0042 recites “Although up/down counter was described with reference to FIG.3B, other implementations may employ other techniques to controllably adjust the delay to effect current balance among the phase currents. Some embodiments may implement a controlled delay using, for example, voltage sensitive varactors or switched capacitor network to form, for example, a programmable delay line. Some embodiments may implement an adjustable delay using a ramp/threshold comparison circuit, for example.”].
Claim Rejections - 35 USC § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
11. Claim(s) 14 and 20 - 21 are rejected under 35 U.S.C. 103 as being unpatentable over McKenzie in view of US Pub. No. 2025/0158526 A1; (hereinafter Mckenzie and D’Souza et al).
Regarding claim 14, McKenzie [e.g., Figs. 1 - 4B] discloses wherein the first control signal is a first pulse width modulation control signal [e.g., PWM1 (130_1)]; wherein the first power converter controller is operative to control the magnitude of the first output current based on the first pulse width modulation control signal received from the current controller [e.g., SPS1 controls output current Iout1 of SW1 from PWM_1 received from PWM Controller 125].
However, McKenzie does not disclose wherein the second power converter controller is operative to control the magnitude of the second output current based on the first pulse width modulation control signal received from the current controller.
D’Souza et al [e.g., Figs 1 - 8] teaches wherein the second power converter controller [e.g., -- refer to Fig. 3A for power stage 300 --, sub-stage 320] is operative to control the magnitude of the second output current based [e.g., controls SW of sub-stage 320] on the first pulse width modulation control signal received from the current controller [e.g., PWMNB-1 signal (216)].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify McKenzie with wherein the second power converter controller is operative to control the magnitude of the second output current based on the first pulse width modulation control signal received from the current controller as suggested by D’Souza et al to control both stages with the same PWM signal as reduce total overall components.
Regarding claim 20, Mckenzie does not disclose implement a first current starved inverter circuit to convert the first control signal into the second control signal, the first current starved inverter circuit operative to control timing of a leading edge of the second control signal; and implement a second current starved inverter circuit to convert the first control signal into the second control signal, the second current starved inverter circuit operative to control timing of a trailing edge of the second control signal.
D'Souza et al [e.g., Fig. 8] teaches implement a first current starved inverter circuit to convert the first control signal into the second control signal [e.g., implements first PWM interface 570 (modulator) to convert PWMB-1 (216) to signal 571], the first current starved inverter circuit operative to control timing of a leading edge of the second control signal [e.g., controls timing of leading edge of signal 571 (when DN is a logic high (UP being a logic low)), p. 0094 recites “FIG. 8 is a diagram illustrating the details of PWM interface 570 (modulator) in an embodiment of the present disclosure. PWM interface 570 is shown containing current sources 810 and 820, P-channel MOSFET (PMOS) 830, N-channel MOSFET (NMOS) 840 and inverter 850. The currents through current sources 810 and 820 are respectively determined by signals UP (575) and DN (576), which are generated within PWM interface 570 (as noted above). … On the other hand, when DN is a logic high (UP being a logic low), the current through 820 is increased (and therefore larger than that through 810). As a result, the rising-edge of PWMB-1 is delayed by a corresponding duration, thereby decreasing the pulse-width (here logic-HIGH duration) of signal 571.”]; and implement a second current starved inverter circuit to convert the first control signal into the second control signal [e.g., implements first PWM interface 570 (modulator) to convert PWMB-1 (216) to signal 571], the second current starved inverter circuit operative to control timing of a trailing edge of the second control signal [e.g., controls timing of leading edge of signal 571 (when UP is a logic high (DN being a logic low)), p. 0094 recites “When UP is a logic high (DN being a logic low), the current through 810 is increased (and therefore larger than that through 820). As a result, the falling-edge of PWMB-1 is delayed by a corresponding duration, thereby increasing the pulse-width (here logic-HIGH duration) of signal 571.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify McKenzie with implement a first current starved inverter circuit to convert the first control signal into the second control signal, the first current starved inverter circuit operative to control timing of a leading edge of the second control signal; and implement a second current starved inverter circuit to convert the first control signal into the second control signal, the second current starved inverter circuit operative to control timing of a trailing edge of the second control signal as suggested by D’Souza et al to provide a higher precision of adjustment to the PWM signals.
Regarding claim 21, McKenzie [e.g., Figs. 1 - 4B] discloses wherein a magnitude of a first delay amount provided to control the timing of the leading edge of the second control signal [e.g., magnitude of leading edge delayed PWMi signal] is based on a first error signal [e.g., -- refer to Fig. 3B --, first difference signal 365a via first comparator 360a] representing a difference between a target value of controlling the magnitude of the first output current with respect to a measured magnitude of the first output current [e.g., based on difference between voltage VA indicates current level of delivered output by SPSi, p. 0027 recites “When the difference between the reference voltage VREFIN and the amplified voltage (e.g., VA) is positive and exceeds the first predetermined dead zone, the first control signal 365a may imply that the current of SPSi is above an average current (e.g., IMONi>IMON/N).” and VREFIN, p.0024 recites “the voltage source 310 may be a signal generated by an SPS1 that represents a scaled version of the output current Iouti (e.g., the current through inductor 140)”]; and wherein a magnitude of a second delay provided to control the timing of the trailing edge of the second control signal [e.g., magnitude of trailing edge delay PWMi signal] is based on a second error signal [e.g., 365b via second comparator 360b] representing a difference between the measured magnitude of the first output current with respect to the target value of controlling the magnitude of the first output current [p. 0028 recites “The second control signal 365b may imply that the current of SPSi is below the average current (e.g., IMONi<IMON/N). In some embodiments, the range of the first predetermined dead zone may be equal to the range of the second predetermined dead zone.” Additionally p. 0044 recites “In some implementations, a detection circuit in one of the stages (SPS) may determine a sign and/or magnitude of a difference between the stage phase current and an average of phase currents in all stages.”].
However, McKenzie does not disclose the first current starved inverter circuit and the second current starved circuit.
D’Souza et al teaches the first current starved inverter circuit [e.g., PWM Interface 570 corresponding to sub-stage 310] and the second current starved circuit [e.g., PWM Interface 570 corresponding to sub-stage 320].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify McKenzie with the first current starved inverter circuit and the second current starved circuit as suggested by D’Souza et al to provide a higher precision of adjustment to the PWM signals. Additionally, McKenzie suggests p. 0042 recites “Although up/down counter was described with reference to FIG.3B, other implementations may employ other techniques to controllably adjust the delay to effect current balance among the phase currents. Some embodiments may implement a controlled delay using, for example, voltage sensitive varactors or switched capacitor network to form, for example, a programmable delay line. Some embodiments may implement an adjustable delay using a ramp/threshold comparison circuit, for example.”
Examiner’s Note
12. Examiner has cited particular paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
13. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
14. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US Pub. No. 2004/0146101 A1 (Pearce) discloses a digitally-implemented pulse width modulation (PWM) signal generator forms the PWM pulse width as a rational number based on full cycles of a PWM reference clock, and offers a very high effective resolution of the PWM pulse signal that is compatible with multiphase DC-DC converters.
US Pub. No. 2013/0057239 A1 (Kalje et al) discloses a multi-phase power block for a switching regulator includes a phase control circuit, N power cells and a current sharing control circuit
US Pub. No. 2015/0333629 A1 (Jang et al) discloses a multi-phase interleaved converter includes n sub-circuits of phases, a current controller and a balancing controller.
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/MONICA LEWIS/Supervisory Patent Examiner, Art Unit 2838
/ULARISLAO CORDOVA/ Examiner, Art Unit 2838
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