DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 13, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent No. 6,395,5438 to Bruce et al. (“Bruce”).
As to independent claim 1 and similarly recited independent claim 13 and 20, a circuit layout processing method/apparatus/CRM (Fig. 7: 700, 703, 1:5-10), the method comprising: obtaining an initial circuit layout of a chip, the initial circuit layout including initial position information of a line in the chip (2:58-67, 3:1-29, Fig. 1A, 1D, 2A. Bruce teaches obtaining original digital IC design shapes data representing an IC layout, wherein the original shapes data defines lines and their edges, including the original positions/placements of those edges.); obtaining a correction value of the line, the correction value being set based on an etching processing error of the chip (3:30-64,8:56-59, Fig. 2A-2B. Bruce teaches obtaining, for a line segment, a correction/adjustment value specifying how far the line or its edge should be shifted, wherein the correction values predict deviations caused by etching and may be derived from the measured difference between original pattern dimensions and dimensions after etching.); and correcting, by processing circuitry, a boundary of the line in the initial circuit layout based on the initial position information and the correction value to obtain a corrected circuit layout (3:9-17, 30-42, 65-67, 4:1-5, 6:62-67, 7:1-34, 8:44-52, Fig. 1D, 2A, 6, 7. Bruce teaches using computer processing to apply an etch bias correction amount to the original position of a line edge, thereby shifting the boundary of the line and producing adjusted/corrected IC design shapes data. Bruce’s method is implemented as computer readable instructions executed by processor 710.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bruce in view of US Patent No. 6,816,170 to Udeshi (“Udeshi”).
Bruce teaches correcting an original IC layout line boundary using an etch bias correction value derived from etching induced dimensional deviation, but does not expressly teach varying that boundary correction based upon whether the layout feature contains a hole.
Udeshi teaches circuit layout geometry is commonly represented by polygons that my contain holes, teaches identifying/separating hole geometry from the outer polygon geometry, and teaches performing the boundary resizing operation differently when holes are present, specifically, treating the outer boundary and the hole boundaries in opposite resizing direction (1:15-24, 35-44, 11:45-67, 12:1-5,31-40,62-67, 13:1-21, Fig. 6, 7A.)
It would have been obvious to a PHOSITA to apply Udeshi’s known hole aware polygon sizing technique to Bruce’s etch bias boundary correction so that Bruce’s etch derived correction value could accurately correct a circuit layout feature containing a hole. Doing so permits the etch derived correction to be applied to both the exterior and interior boundaries while preserving the intended topology of the feature.
Claims 3, 4, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Bruce in view of US Pub. No. 2007/0234260 to Gonzalez et al. (“Gonzalez”).
As to claims 3 and 15, Bruce teaches original IC layout/design containing line segments and line edges and obtains an etch bias corrective parameter specifying an amount by which the original line geometry is be shifted (3:18-42, Fig. 2A). Bruce teaches applying the correction amount to the original line geometry by shifting the original line edges, thereby producing an adjusted or corrected original shapes data set (3:8-17, 61-67, 4:1-5, Fig. 1D, 2A). Bruce also teaches generating marker shape geometry corresponding to portions of the original IC design, overlaying those marker shapes with the original design, and using the marker shape regions to identify the edges to which particular etch bias corrections are applied (5:15-60, Fig. 3, claim 3).
Bruce therefore teaches both boundary correction using an etch driven correction value and the use of separate geometric marker regions to control correction of original line edges (3:18-42, 61-67, 4:1-5, 5:15-60, Fig. 2A-3, claim 3).
Bruce, however, does not teach the full limitation of “generating a correction box of the boundary of the line in the initial circuit based on the initial position information and the correction value”.
In particular, Bruce’s marker shapes are generated from region definitions/design characteristics, not from the geometric difference produced by applying the correction value to the original boundary (5:15-35). Bruce associates an etch bias with the marker region after the marker region is defined, Bruce does not disclose generating dimensions/geometry of the marker shape from both the original boundary position and the correction amount.
Accordingly, the gap in Bruce is the claimed intermediate correction geometry: a correction box whose geometry is generated based on the original boundary position and correction value and which is then used to modify the original layout.
Gonzalez is directed to modification of VLSI design layouts (¶ 0001, 0014). Gonzalez teaches retaining original VLSI layout shapes and generating revised layout shapes representing desired modifications to the original layout (¶ 0016, 0017). Gonzalex teaches determining the geometric differences between the original and revised shapes through geometric, shape wise Boolean operations and representing those differences as ADD and HOLE correction shapes (¶ 0018). Gonzalex teaches combining those ADD and HOLE correction shapes to form a separate overlay cell representing the changes between the original and revised layout geometries (¶ 0018, Fig. 1). Gonzalex further teaches applying the overlay correction shapes to the original shapes to produce the final modified layout (¶ 0019). Gozalez’s specific example confirms that revised shape 302 is superimposed on the original shape 202 to generate ADD and HOLE regions, with ADD shapes 502 added to and HOLE shapes 504 subtracted from the original mask geometry (¶ 0021, Fig. 3-5).
Thus, Gonzalez teaches generating an intermediate geometric correction structure from the geometric difference between original and revised layout boundaries and thereafter using that correction structure to modify the original layout into the final revised layout.
It would have been obvious to a PHOSITA to modify Bruce such that, after Bruce determines a corrected line boundary from the original boundary position and the etch derived correction value, a separate correction geometry representing the geometric difference between the original and corrected boundaries is generated according to Gonzalez and applied to the original layout to produce the correct circuit layout. The PHOSITA would have been motivated to make this modification because Gonzalez expressly teaches that its separate overlay technique permits layout changes to be implemented while leaving the original layout data unchanged and provides a non-disruptive mechanism for introducing such changes to existing VLSI design and mask building flow (Gonzalez: 0004, 0016-0019, 0021, 0022, Fig. 1, 3-5, Bruce: 3:8-42, 61-67, 4:1-5).
As to claim 4 and similarly recited claim 16, the method according to claim 3, wherein the correcting the boundary of the line in the initial circuit layout based on the correction box comprises: performing a Boolean operation based on the initial position information and position information of the correction box to obtain the corrected circuit layout (Bruce: 5:31-60, Gonzalez: ¶ 0018-0019, 0021, 0022, Fig. 1, 4-5. Gonzalez teaches performing Boolean geometric operations using the original layout geometry and the separately generated overlay correction geometry and combining those geometries to produce the final modified layout.).
Claims 5, 6, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Bruce in view of Gonzalez and in further view of Udeshi.
Bruce in view of Gonzalez teaches adding/merging ADD correction geometry with original layout geometry and substracting HOLE correction geometry from original layout geometry (Gonzalez: ¶ 0018, 0019, 0021, Fig. 4, 5). Bruce in view of Gonzalez, however, does not expressly teach the limitations of claims 5, 6, 17, and 18.
Udeshi teaches that a positive correction/resize value indicates an outward offset, while a negative correction/resize value indicates an inset (12:50-62, Fi.g 7A). Accordingly, the combined teachings provide merging correction geometry with the original geometry when the correction value is positive, as recited by claim 5, and subtracting correction geometry from the original geometry when the correction value is negative, as recited by claim 6.
It would have been obvious to a PHOSITA to modify the Bruce/Gonzalez method/apparatus to use Udeshi’s known sign convention such that a positive correction value selects Gonzalez’s additive/merge operation and a negative correction value selects Gonzalez’s subtractive operation. The PHOSITA would have been motivated to make the modification because Udeshi expressly teaches using the sign of the resize value to identify whether the desired geometric correction is an outward offset or an inward inset, thereby providing a straightforward and predictable mechanism for selecting the corresponding additive or subtractive Boolean operation already taught by Gonzalez.
Claims 7-9, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Bruce in view of Gonzalez and in further view of Udeshi.
As to claims 7 and 19, Bruce in view of Gonzalez does not expressly teach the limitations of claims 7 and 19.
Udeshi teaches determining whether hole geometry exists by comparing the original polygon with its outer boundary and identifying the resulting hole component(s) (11:45-67, 12:1-5, Fig. 6). Udeshi further teaches generating the corrected/resized geometry according to the detected presence of holes by processing the outer and inner boundaries differently (12:31-40, 62-67, 13:1-21, Fig. 6, 7A).
It would have been obvious to a PHOSITA to modify the Bruce/Gonzalez method/apparatus so that Gonzalez’s correction geometry is generated according to Udeshi’s determined hole information, with the correction geometry accounting for the outer and inner boundaries when a hole is detected. The PHOSITA would have been motivated to make the modification because Udeshi expressly teaches this hole aware processing to accurately resize polygonal geometry containing holes (11:45-67, 12:1-5, 31-40, Fig. 6, 7A).
As to claim 8, the method according to claim 7, wherein the generating the correction box based on the initial position information and the correction value according to the hole detection information comprises: adding, when the hole detection information indicates that no hole exists in the line, the correction value based on the initial position information of the boundary of the line to obtain the correction box (Udeshi teaches that, for geometry without a hole, the original boundary positions are displaced by the correction/offset distance d to obtain revised boundary positions (7:17-31, Fig. 1A-1B). Gonzalez teaches representing the geometric difference between the original and revised boundaries as the overlay correction geometry relied upon as the claimed correction box (¶ 0018, 0021, Fig. 4, 5). Accordingly, the combined teachings provide adding the correction value to the initial boundary position information, when no hole exists, to obtain the correction box as recited by claim 8.).
As to claim 9, the method according to claim 7, wherein the generating the correction box based on the initial position information and the correction value according to the hole detection information comprises: segmenting, when the hole detection information indicates that the line has the hole, the boundary of the line to obtain at least one outer boundary box and at least one inner boundary box, the outer boundary box corresponding to an outer boundary of the line, and the inner boundary box corresponding to a boundary of the hole in the line; adding, based on position information of the at least one outer boundary box, the correction value to the at least one outer boundary box to obtain at least one outer boundary correction box; subtracting, based on position information of the at least one inner boundary box, the correction value from the at least one inner boundary box to obtain at least one inner boundary correction box; and obtaining the correction box based on the at least one outer boundary correction box and the at least one inner boundary correction box (Udeshi teaches separating polygon geometry into an outer boundary and inner/hole boundary geometry, applying the correction distance outward to the outer boundary and inward to the hole boundary, and combining the corrected outer and inner geometries to form the resulting corrected polygon (11:45-67, 12:1-5, 62-67, 13:1-21, Fig. 6, 7A). In view of Gonzalez’s correction box teaching discussed above, the combined references therefore teach obtaining the correction box from the separately corrected outer boundary and inner boundary geometries, as recited by claim 9.).
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Bruce in view of US Pub. No. 2022/0029266 to Yu et al. (“Yu”).
Bruce does not expressly teach the limitations of claims 11 or 12.
Yu teaches a superconducting quantum chip (¶ 0002, 0003, 0032, 0073). Yu further teaches a quantum chip layout containing coplanar waveguides, including transmission line structures formed from coplanar waveguides (¶ 0038, 0052, 0053, 0074).
It would have been obvious to a PHOSITA to apply Bruce’s known etch bias layout correction method to the superconducting quantum chip layout taught by Yu, including Yu’s coplanar waveguide lines, so that the intended quantum chip line geometry is compensated for dimensional deviation introduced during etching. Yu expressly teaches a superconducting quantum chip having a circuit layout structure and coplanar waveguide features, while Bruce teaches correcting IC layout line boundaries to compensate for etch bias. Applying Bruce’s known correction technique to Yu’s patterned quantum chip layout would therefore have been a predictable use of a known fabrication layout correction technique on a similar lithographically defined circuit geometry.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 10 would be allowable if amended in the manner above because the prior art of record does not teach or suggest a method having all the steps or elements as recited in and required by claim 10.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner SURESH MEMULA whose telephone number is (571)272-8046, and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email (suresh.memula@uspto.gov) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300.
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/SURESH MEMULA/Primary Examiner, Art Unit 2851
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