Prosecution Insights
Last updated: May 29, 2026
Application No. 18/638,649

STATION MULTI-LINK DEVICE AND OPERATION METHOD THEREOF

Non-Final OA §103
Filed
Apr 17, 2024
Priority
May 05, 2023 — TW 112116788
Examiner
RUTKOWSKI, JEFFREY M
Art Unit
2415
Tech Center
2400 — Computer Networks
Assignee
Realtek Semiconductor Corp.
OA Round
3 (Non-Final)
67%
Grant Probability
Favorable
3-4
OA Rounds
2y 0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
219 granted / 328 resolved
+8.8% vs TC avg
Strong +31% interview lift
Without
With
+31.0%
Interview Lift
resolved cases with interview
Typical timeline
4y 2m
Avg Prosecution
3 currently pending
Career history
342
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
86.0%
+46.0% vs TC avg
§102
2.8%
-37.2% vs TC avg
§112
9.8%
-30.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 328 resolved cases

Office Action

§103
DETAILED ACTION Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/22/2026 has been entered. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Naribole et al. (US 11,690,012 B2) (hereinafter Naribole in view of Cherian et al. (US 2018/0206190 A1) (hereinafter Cherian) and Asterjadhi et al. (US Pg Pub 2019/0007904), hereinafter referred to as Asterjadhi. Regarding Claims 1 and 15, Naribole teaches: A station multi-link device (STA MLD), the station multi-link device comprising N radio chains, M antennas, and a processor, the processor being coupled to the N radio chains, N and M being positive integers, M≥N, the method comprising: the processor setting the station multi-link device to a multi-link multi-radio (MLMR) mode; (Naribole, Fig. 3, col. 3, lines 15-40; Col. 5, lines 5-25) Naribole discloses multi-radio parallel operation across independent links. the processor setting each radio chain to transmit or receive data via the M antennas; (Naribole, Fig. 3, Col. 5, lines 5-25) Naribole discloses multi-radio parallel operation across independent links. the processor setting a power save mode of at least one radio chain to a doze state; (Naribole, Fig. 5, Col. 6, lines 25-55: See steps 506-508) Processor places at least one link in doze mode based on operating conditions. Thus, Naribole does not explicitly teach the processor allocating the M antennas to the N radio chains according to an application scenario; and (Cherian, Fig. 7, [0074]- [0075], [0091]- [0100]) Cherian teaches application-aware link and antenna management based on real time metrics (latency, throughput, etc.), including load balancing and link activation driven by application context. the processor updating N power save modes of the N radio chains according to the application scenario. (Naribole, Fig. 5, col. 6, lines 25-65); (Cherian, fig. 6, fig. 7, [0083-0095]) Naribole demonstrates the power control, but not in response to specific application types. However, Cherian teaches per-link power control (Receiver Powering Manger 730, Channel Conditions Manager 760) based on runtime triggers such as latency or traffic type. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Naribole’s multi-radio platform with Cherian's application-aware control system. The combination allows dynamic link management and power/antenna allocation responsive to system performance needs, a predictable and beneficial enhancement in wireless multi-link architecture. Naribole does not disclose the use of full duplexing. Asterjadhi discloses the processor configuring each radio chain (transceiver 214) to transmit or receive data via all the M antennas (item 216) simultaneously (see figure 2; the antennas communicate simultaneously over WUR and main communication channels; see paragraph 0155). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Asterjadhi’s arrangement in Naribole’s invention make use of different radio states (Asterjadhi, paragraph 0155). Specifically for claim 15, Naribole does not explicitly teach when the application scenario is throughput-oriented, the processor allocating the M antennas to one of the N radio chains, wherein a connection of the radio chain is better than connections of other radio chains of the N radio chains (this feature is not given patentable weight. The claim allows for both M and N to be equal to one. In the situation where there is a singular radio chain with a singular antenna, there are no “other radio chains”). (Cherian, Fig. 12, [0125]- [0127]) Cherian teaches high-throughput performance, the system selectively activates the best performance, the system selectively activates the best-performing link and reallocates communication resources to it. Paragraph [0125] and figure 12 describe how the STA chooses and prioritizes the link with the highest quality connection for data transmission. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Naribole’s dynamic antenna and radio chain control with Cherian’s teaching of concentrating communication resources on the best-performing link under high-throughput demand. Doing so would lead to predicable improvements in system efficiency and performance, a routine optimization in design of multi-radio wireless communication systems. Regarding Claim 2, Naribole teaches the method of Claim 1. wherein the processor updating the N power save modes of the N radio chains according to the application scenario comprises: (Naribole, Fig. 5, Col. 6, lines 25-65: See steps 504-508); (Cherian, fig. 7, [0083]- [0095], [0099]- [0100]) Naribole teaches that the processor adjust power states of each radio chain in response to system usage and traffic demand. Thus, Naribole does not explicitly teach when the application scenario is latency-oriented, the processor setting the N power save modes of the N radio chains to an awake state. (Cherian, Fig. 7, [0094]- [0100]) Cherian teaches that when latency-sensitive applications are active, multiple wireless links are simultaneously transitioned to active state. Figure 7 shows a system in which power managers (730, 745) and the channel conditions manager (760) control activation based on traffic type and runtime parameters. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Naribole’s link-level power control with Cherian's latency-driven link activation logic. Doing so would enable the system to keep all radios active when necessary to meet low-latency communication demands, which is predictable design decision for ensuring real-time performance. Regarding Claim 3, Naribole teaches the method of Claim 1. wherein the processor allocating the M antennas to the N radio chains according to the application scenario comprises: (Naribole, Fig. 5, Col. 13, lines 20-45: See steps 502-504) Naribole teaches dynamic radio chain and antenna resource management based on performance conditions. Cherian provides latency-sensitive scheduling techniques using load balancing across available links. Thus, Naribole does not explicitly teach when the application scenario is latency-oriented, the processor evenly allocating the M antennas to the N radio chains. However, in analogous art Cherian provides the teachings balanced resource activation to meet low-latency requirements (Cherian, Fig. 9, [0109]). Cherian describes evenly allocating communications resources across all available links for latency-sensitive applications. Paragraph [0109] explain that link scheduling is adapted to ensure minimal delay, Figure 9 shows active link management modules working in parallel to support balanced operation. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Naribole’s application-aware antenna assignment with Cherian’s latency-optimized allocation logic. Doing so would result in even distribution of antennas across radio chains in latency-oriented scenarios, yielding predictable benefits in minimizing transmission delay and balancing communication load, a well-understood design goal in wireless system optimization. Regarding Claim 4, Naribole teaches the method of Claim 1. wherein the processor updating the N power save modes of the N radio chains according to the application scenario comprises: (Naribole, Fig. 5, Col. 13, lines 40-45, Col. 14, lines 30-45, Col. 15, lines 5-25) Naribole teaches the processor updates radio chain power states based on traffic or system performance triggers. Thus, Naribole does not explicitly teach when the application scenario is throughput-oriented, the processor setting a power save mode of one of the N radio chains to an awake state, wherein a connection of the radio chain is better than connections of other radio chains of the N radio chains. (Cherian, Fig. 12, [0125]) Cherian teaches activating only the best-performing link for communication in high-throughput scenarios. Paragraph [0125] and figure 12 describe the selective activation of one radio chain based on connection quality to optimize performance. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Naribole’s power sav control strategy with Cherian’s performance-based link selection logic. Doing so would allow the system to selectively activate the radio chain with the best connection during throughput-oriented operation, a predicable design choice aimed at maximizing data efficiency in multi-link wireless system. Regarding Claim 5, Naribole teaches the method of Claim 1. wherein the processor allocating the M antennas to the N radio chains according to the application scenario comprises: (Naribole, Fig. 5, Col. 13, lines 20-45, Col. 14, lines 30-45, Col. 15, lines 5-25: See steps 502-506) Naribole teaches antenna and radio chain resources are managed dynamically based on system traffic and control logic Thus, Naribole does not explicitly teach when the application scenario is throughput-oriented, the processor allocating the M antennas to one of the N radio chains, wherein a connection of the radio chain is better than connections of other radio chains of the N radio chains. (Cherian, Fig. 12, [0125]- [0127]) Cherian teaches high-throughput performance, the system selectively activates the best performance, the system selectively activates the best-performing link and reallocates communication resources to it. Paragraph [0125] and figure 12 describe how the STA chooses and prioritizes the link with the highest quality connection for data transmission. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Naribole’s dynamic antenna and radio chain control with Cherian’s teaching of concentrating communication resources on the best-performing link under high-throughput demand. Doing so would lead to predicable improvements in system efficiency and performance, a routine optimization in design of multi-radio wireless communication systems. Regarding Claim 6, Naribole teaches the method of Claim 1. wherein the processor updating the N power save modes of the N radio chains according to the application scenario comprises: (Naribole, Fig. 5, Col. 13, lines 20-45, Col. 14, lines 1-15, Col. 15, lines 5-25: See steps 600-610) Naribole teaches dynamic link-level power save updates based on performance requirements. Cherian teaches activating all radios to support latency-and throughput-sensitive operations. Thus, Naribole does not explicitly teach when the application scenario is joint throughput-latency-oriented, the processor setting the N power save modes of the N radio chains to an awake state. (Cherian, Fig. 7, Fig. 12, [0053]- [0054], [0109]) Cherian teaches that when both high throughput and low latency are needed, the system activates all available links to maximize responsiveness and bandwidth. Paragraphs [0053]- [0054] explain that multi-radio aggregation techniques enable concurrent link activation. Paragraph [0109] and figures 7 and 12 show fully awake link states in high-performance modes Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Naribole’s dynamic power save management with Cherian’s full-ink activation strategy under joint performance constrains. Doing so would allow the processor to set all N radio chains to an awake state in response to simultaneous throughput and latency demands, a predictable enhancement that improves responsiveness and data delivery, aligned with routine optimization in wireless multi-link system design. Regarding Claim 7, Naribole teaches the method of Claim 1. wherein the processor allocating the M antennas to the N radio chains according to the application scenario comprises: (Naribole, Fig. 5, Col. 13, lines 20-45, Col. 14, lines 30-45: See steps 502-506) Naribole shows dynamic allocation of radio and antenna resources in response to control logic triggered by traffic and performance demands. Thus, Naribole does not explicitly teach when the application scenario is joint throughput-latency-oriented, the processor unevenly allocating the M antennas to the N radio chains. (Cherian, Fig. 9, [0083]) Cherian describes that for combined performance goal (high throughput and low latency), the system may assign more antennas or resources to specific links based on quality or responsiveness needs. This implies non-uniform (uneven) resource allocation depending on which link contributes most to overall performance. Figure 9 and paragraph [0109] support this by showing differentiated link handling based on runtime conditions. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Naribole’s application-driven antenna management with Cherian’s asymmetric, performance-based antenna allocation. Doing so would enable the processor to respond to dual throughput- latency demands by concentrating antenna resources on selected radio chains, a predictable and well-understood optimization in multi-link systems for latency-critical high-bandwidth communication. Regarding Claim 8, Naribole teaches: A station multi-link device (STA MLD) comprising: N radio chains, N being a positive integer; (Naribole, Fig. 3, Col. 5, lines 5-25) Naribole teaches device 104 with multiple radios and antennas under the control of a processor. M antennas coupled to the N radio chains, (Naribole, Fig 3) Radios 302a-b are examples of multiple radio chains. M being a positive integer, M≥N; and (Naribole, Fig. 3, Col. 5, lines 5-25) Antennas 300a-b are connected to the radios. a processor coupled to the N radio chains, (Naribole, Fig. 3, Col. 5, lines 15-25) Naribole teaches processor 304 controls radios 302a/b and configured to set the station multi-link device to a multi-link multi-radio (MLMR) mode, (Naribole, Fig. 4, Col. 3, lines 15-40) Naribole teaches parallel multi-link operation is supported. set each radio chain to transmit or receive data via the M antennas, (Naribole, Fig. 4, Col. 5, lines 15-40) Naribole teaches radio transmit/receive via connected antennas. set a power save mode of at least one radio chain to a doze state, (Naribole, Fig. 5, Col. 6, lines 25-55: See step 508) Naribole teaches a link is placed in doze state while others are disabled. Thus, Naribole does not explicitly teach allocate the M antennas to the N radio chains according to an application scenario, (Cherian, Fig. 7, [0091]- [0100]) Cherian teaches that link radio activity is reassigning based on application context such as latency or throughput need, which implies antenna reallocation. and update N power save modes of the N radio chains according to the application scenario. (Cherian, Fig. 6, Fig. 7, [0083]- [0095]) Cherian teaches power saves states are modified using modules like the Receiver Powering Manager and Channel Conditions Manager, which adjust link activity based on traffic type or performance metrics. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Naribole’s multi-radio platform with Cherian's adaptive, application-aware control systems. The result is a device that dynamically manages its radios and antennas in response to performance needs, an expected improvement in wireless link management. Naribole does not disclose the use of full duplexing. Asterjadhi discloses the processor configuring each radio chain (transceiver 214) to transmit or receive data via all the M antennas (item 216) simultaneously (see figure 2; the antennas communicate simultaneously over WUR and main communication channels; see paragraph 0155). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Asterjadhi’s arrangement in Naribole’s invention make use of different radio states (Asterjadhi, paragraph 0155). Regarding Claim 9, Naribole teaches the method of Claim 8. (Naribole Fig.3; Col. 5, lines 5-25) Naribole teaches STA MLD with multiple radios, antennas, and a processor with all prior configurations. wherein when the application scenario is latency-oriented, (Naribole, Fig. 3, Fig. 5, Col. 13, lines 40-67, Col. 14, lines 1-15) Naribole discusses adjusting system behavior (link activity, antenna control) in response to traffic and performance needs, which may correspond to latency-oriented scenarios. Thus, Naribole does not explicitly teach the processor is configured to set the N power save modes of the N radio chains to an awake state. (Cherian, Fig. 9, [0083]) Cherian teaches that in latency- sensitive scenarios, the processor transitions all available links the active state to reduce delay and improve responsiveness. Paragraph [0083] and Figure 9 describe full activation of links from low-power states when real-time performance is required. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Naribole’s device-level power management with Cherian’s teaching of fully waking all links in latency-oriented scenarios. Doing so would allow processor to actively configure all radio chains in awake mode when latency is prioritized, resulting in lower transmission delays and improved user experience, a routine optimization in multi-link system design. Regarding Claim 10, Naribole teaches the method of Claim 8. wherein when the application scenario is latency-oriented, (Naribole, Fig. 3, Fig. 5, Col. 13, lines 40-67, Col. 14, lines 1-15) Naribole describes adjusting antenna usage and radio chain activity based on traffic conditions. In latency-sensitive environments, antenna resources may be distributed across active links to maintain performance. Thus, Naribole does not explicitly teach the processor is configured to evenly allocate the M antennas to the N radio chains. (Cherian, Fig. 9, [0083]) Cherian Discusses symmetric activation of links and balanced resource usage in latency-sensitive scenarios. Paragraph [0083] and Figure 9 show uniform link activation to handle real-time communication needs, which implies even antenna allocation across radio chains. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Naribole’s dynamic antenna and radio chain management with Cherian's context-driven symmetrical link activation. Doing so would support even antenna distribution in latency-driven conditions, a predictable and routine system design choice aimed at minimizing communication delays. Regarding Claim 11, Naribole teaches the method of Claim 8. wherein when the application scenario is throughput-oriented, the processor is configured to set a power save mode of one of the N radio chains to an awake state, (Naribole, Fig. 5, Col. 9, lines 20-36, Col. 10, lines 1-10) Naribole disclose transitioning radio chains between doze and awake states depending on system traffic. The processor enables link activation when needed to maintain performance, reflecting a throughput-oriented control scheme. Thus, Naribole does not explicitly teach wherein a connection of the radio chain is better than connections of other radio chains of the N radio chains. (Cherian, Fig. 12, [0125]- [0127]) Cherian teaches activating the best-performing link under throughput demands. Paragraph [0125] explains that the processor evaluates link performance metrics (e.g., channel quality) to determine which radio chain to activate. Paragraph [0127] further reinforces that this selection is based on signal strength, throughput, and reliability, and Figure 12 illustrates this targeted activation process. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Naribole’s power save control logic with Cherian’s performance-based link selections strategy. Doing so would enable the processor to prioritize and wake only the best-connected radio chain during throughput-intensive operations, a predicable improvement that enhances data transmission efficiency in multi-link devices. Regarding Claim 12, Naribole teaches the method of Claim 8. wherein when the application scenario is throughput-oriented, the processor is configured to allocate the M antennas to one of the N radio chains, (Naribole, Fig. 5, Col. 9, lines 20-36, Col. 9, lines 55-65) Naribole teaches that the processor manages radio chain activation and antenna control based on traffic demands. It shows enabling/ disabling radios and adjusting antenna usage under varying system profiles. However, it does not teaches allocating all M antennas to a single radio chain during throughput-oriented operation. Thus, Naribole does not explicitly teach wherein a connection of the radio chain is better than connections of other radio chains of the N radio chains. (Cherian, Fig. 12, [0125]- [0127]) Cherian describes a throughput-prioritized system in which the processor selects the best-performing link based on signal quality, channel strength, or throughput. Paragraph [0125] explains selecting the optimal link to maximize performance, and paragraph [0127] confirms the decision is based on comparative link metrics. Figure 12 illustrates focused transmission through the strongest link. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Naribole’s antenna reassignment logic with Cherian’s throughput-optimized allocation. Doing so would enable the processor to dynamically assign all antenna resources to the most efficient chain under high-throughput demand, resulting in predicable improvements in system efficiency and performance, a well-known objective in the design of multi-radio wireless systems. Regarding Claim 13, Naribole teaches the method of Claim 8. wherein when the application scenario is joint throughput-latency-oriented, (Naribole, Fig. 5, Col. 9, lines 20-36, Col. 10, lines 1-10) Naribole teaches the dynamic power state control, where the processor adjust link activity depending on throughput needs or application profiles. Links may enter or exit doze states in response to traffic conditions. Thus, Naribole does not explicitly teach the processor is configured to set the N power save modes of the N radio chains to an awake state. (Cherian, Fig. 7, Fig. 12, [0053]- [0054]) Cherian describes activating multiple radio links simultaneously to satisfy performance-sensitive applications involving both high data rates and real-time responsiveness. Paragraph [0053]- [0054] describe multi-radio aggregation to support high-throughput, low latency demands. Paragraph [0109] reinforces the activation of all links in latency-sensitive cases, and Figures 7 and 12 illustrate full-link activation under such performance-critical conditions. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Naribole’s traffic-aware power control with Cherian's strategy of keeping all radios active in dual-demand scenarios. Doing so would predicably improve responsiveness and bandwidth, a routine and expected outcome in multi-link wireless device design. Regarding Claim 14, Naribole teaches the method of Claim 8. wherein when the application scenario is joint throughput-latency-oriented, (Naribole, Fig. 5, Col. 9, lines 20-36, Col. 10, lines 1-10) Naribole describes selective link activation and antenna control based on traffic levels, power conservation, and operational transitions. The system enables different links depending on detected conditions, allowing dynamic role assignment. Thus, Naribole does not explicitly teach the processor is configured to unevenly allocate the M antennas to the N radio chains. (Cherian, Fig. 9, [0083]- [0100]) Cherian teaches differentiated link treatment in systems handling both low-latency and high-throughput traffic. Paragraph [0083] explains that latency-sensitive flows are prioritized over low-latency links, while high-throughput traffic is routed through links with higher capacity. Paragraph [0100] and Figure 9 suggest that resource allocation- including antenna usage – is tailored per link based on performance, implying uneven distribution across radio chains. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Naribole’s context-driven link management with Cherian’s strategy of asymmetric resource allocation. Doing so would lead to a predictable and beneficial system design where antenna resources are concentrated on high-priority links under demanding application scenarios. Response to Arguments Applicant's arguments filed 01/22/2026 have been fully considered but they are not persuasive. The arguments are not commensurate with the scope of the claims. The Applicant’s arguments appear to imply there are multiple N radio chains and multiple M antennas. The claim merely recites there are N radio chains and M antennas with M and N being positive integers. As indicated in the rejection of claim 15, the claims allow for a scenario where M and N are equal to 1 (singular radio chain and singular antenna). The arguments would be persuasive if it was clear there were a plurality of radio chains and a plurality of antennas. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEFFREY M RUTKOWSKI whose telephone number is (571)270-1215. The examiner can normally be reached M-F 9:00 AM - 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Debbie Reynolds can be reached at (571) 272-0734. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JEFFREY M. RUTKOWSKI Supervisory Patent Examiner Art Unit 2415 /JEFFREY M RUTKOWSKI/Supervisory Patent Examiner, Art Unit 2415
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Prosecution Timeline

Apr 17, 2024
Application Filed
May 30, 2025
Non-Final Rejection mailed — §103
Aug 26, 2025
Response Filed
Oct 23, 2025
Final Rejection mailed — §103
Jan 22, 2026
Request for Continued Examination
Jan 29, 2026
Response after Non-Final Action
Apr 21, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
67%
Grant Probability
98%
With Interview (+31.0%)
4y 2m (~2y 0m remaining)
Median Time to Grant
High
PTA Risk
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