Prosecution Insights
Last updated: October 25, 2026
Application No. 18/638,697

SEMICONDUCTOR DEVICE

Final Rejection §103§112
Filed
Apr 18, 2024
Priority
Feb 23, 2024 — TW 113106518
Examiner
SHOOK, DANIEL P
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hon Young Semiconductor Corporation
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
569 granted / 653 resolved
+19.1% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
19 currently pending
Career history
664
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
47.1%
+7.1% vs TC avg
§102
30.6%
-9.4% vs TC avg
§112
15.8%
-24.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 653 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 11-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 11 includes the clause “wherein the source region surrounds the body contact doped region surrounding the source trench structure”, however the body contact doped region is simply disclosed as being comprised by the substrate and is not claimed as surrounding the source trench structure, therefore it is unclear if the claims is intending to be limited to the body contact doped region surrounding the source trench structure as such is implied by the clause regarding the source region but not explicitly claimed with regards to the body contact doped region itself. For examining purposes, the broader interpretation will be applied, that of the body contact doped region simply being present in the substrate and not further limited to surrounding the body contact doped region. Note that such a limitation, more clearly stated, is not found in the prior art of record. Claims 12-20 are rejected for containing the unclear subject matter of claim 11 without remedy. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4, 7-14, 16, 17, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec et al. (US 2016/0064547 A1, hereinafter ‘547) in view of Siemieniec et al. (US 2022/0246744 A1, hereinafter ‘744). Regarding claim 1, ‘547 discloses a semiconductor device (Fig 3A & 3B), comprising: a substrate (100) comprising a drift region (121); a source trench structure (160), in the substrate; a gate trench structure (150), in the substrate, a bottom of the gate trench structure being higher than a bottom of the source trench structure, wherein the gate trench structure surrounds the source trench structure and defines a device unit (TC); and a drain electrode (320), below the substrate. PNG media_image1.png 488 520 media_image1.png Greyscale PNG media_image2.png 536 528 media_image2.png Greyscale ‘547 does not disclose that the substrate comprises a body contact, wherein the source trench structure is separated from the drift region by being surrounded by the body contact doped region, nor the relative projection areas of the source trench and the gate trench along a fixed direction. ‘744 discloses a semiconductor device (Fig 2), comprising a substrate (100) comprising a body contact doped region (140) and a drift region (130); a source trench structure (190), in the substrate, wherein the source trench structure is separated from the drift region by being surrounded by the body contact doped region; a gate trench structure (150), in the substrate; and a drain electrode (320), below the substrate. A shielding region, such as that disclosed by ‘744 serves to modulate the electrical fields that are formed in the power device and therefore enhance the reliability of the device, therefore it would have been obvious to one of ordinary skill in the art at the time of filing to include a shielding region such as that disclosed by ‘744 in the semiconductor device of ‘547 in order to modulate the electrical fields formed during the operation thereof. PNG media_image3.png 742 558 media_image3.png Greyscale ‘547 and ‘744 do not disclose the relative projection areas of the source trench and the gate trench along a fixed direction. It would have been obvious to one of ordinary skill in the art at the time of filing to form the device such that a first projection area of the source trench structure along a fixed direction is less than 20% of a second projection area of the gate trench structure along the fixed direction, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Regarding claim 2, ‘547 and ‘744 do not disclose the relative projection areas of the source trench and the gate trench along a fixed direction. It would have been obvious to one of ordinary skill in the art at the time of filing to form the device such that a first projection area of the source trench structure along a fixed direction is less than 15% of a second projection area of the gate trench structure along the fixed direction, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Regarding claim 3, ‘547 and ‘744 do not disclose the relative projection areas of the source trench and the gate trench along a fixed direction. It would have been obvious to one of ordinary skill in the art at the time of filing to form the device such that a first projection area of the source trench structure along a fixed direction is more than 5% of a second projection area of the gate trench structure along the fixed direction, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Regarding claim 4, ‘547 discloses that the device unit has a shape of hexagon, quadrangle or triangle in a top view. Regarding claim 7, ‘547 discloses that the substrate further comprises: a source doped region (110), between the gate trench structure and the source trench structure. Regarding claim 8, ‘547 discloses a source contact (310) extending from an upper surface of the source doped region to an upper surface of the source trench structure. Regarding claim 9, ‘547 discloses that the source trench structure comprises: a dielectric layer (161); and a conductor layer (165), surrounded by the dielectric layer. Regarding 10, ‘547 discloses that the gate trench structure comprises: a gate dielectric layer (151); and a gate layer (155), surrounded by the gate dielectric layer. Regarding claim 11, ‘547 discloses a semiconductor device (Fig 3A & 3B), comprising: a substrate (100), comprising a source region (110); a source trench structure (160), in the substrate; a gate trench structure (150), in the substrate and adjacent to the source region, a bottom of the gate trench structure being higher than a bottom of the source trench structure, wherein the gate trench structure surrounds the source trench structure and defines a device unit (TC), and an interface between the gate trench structure and the source region of the substrate along a fixed direction is a hexagon; and a drain electrode (320), below the substrate. ‘547 does not disclose that the substrate comprises a body contact, wherein the source trench structure is separated from the drift region by being surrounded by the body contact doped region, nor the relative projection areas of the source trench and the gate trench along a fixed direction. ‘744 discloses a semiconductor device (Fig 2), comprising a substrate (100) comprising a source region (110) and a body contact doped region (140); a source trench structure (190), in the substrate, wherein the source region surrounds the source trench structure; a gate trench structure (150), in the substrate and adjacent to the source region; and a drain electrode (320), below the substrate. A shielding region, such as that disclosed by ‘744 serves to modulate the electrical fields that are formed in the power device and therefore enhance the reliability of the device, therefore it would have been obvious to one of ordinary skill in the art at the time of filing to include a shielding region such as that disclosed by ‘744 in the semiconductor device of ‘547 in order to modulate the electrical fields formed during the operation thereof. Regarding claim 12, ‘547 discloses that the source region is between the gate trench structure and the source trench structure. Regarding claim 13 ‘547 discloses a source contact (310) extending from an upper surface of the source region to an upper surface of the source trench structure. Regarding claim 14, ‘547 discloses that the six sides of the hexagon have substantively the same length. Regarding claim 16, ‘547 and ‘744 do not disclose the relative projection areas of the source trench and the gate trench along a fixed direction. It would have been obvious to one of ordinary skill in the art at the time of filing to form the device such that a first projection area of the source trench structure along a fixed direction is 5% to 20% of a second projection area of the gate trench structure along the fixed direction, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Regarding claim 17, ‘547 and ‘744 do not disclose the relative projection areas of the source trench and the gate trench along a fixed direction. It would have been obvious to one of ordinary skill in the art at the time of filing to form the device such that, in a top view, a first projection area of the source trench structure along a fixed direction is 5% to 15% of a second projection area of the gate trench structure along the fixed direction, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Regarding claim 19, ‘547 discloses that the source trench structure comprises: a dielectric layer (161); and a conductor layer (165), surrounded by the dielectric layer. Regarding claim 20, ‘547 discloses that the gate trench structure comprises: a gate dielectric layer (151); and a gate layer (155), surrounded by the gate dielectric layer. Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over ‘547 in view of ‘744 as applied to claim 1 above, and further in view of Hatada et al. (US 2025/0081548 A1). Regarding claim 5, ‘547 discloses that the device unit has a shape of hexagon in a top view, but does not disclose that the hexagon has a first side and a second side, wherein the first side has a greater length than the second side. Hatada discloses a similar device wherein the device unit has the shape of a hexagon with a first side having a greater length than the second side (Fig 2). Hatada discloses that such a configuration allows for a greater margin for error when contacts are disposed along a given direction (¶64). Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to use an elongated hexagon as disclosed by Hatada as the shape of the device unit in order to realize such a greater margin of error in contact formation. PNG media_image4.png 674 572 media_image4.png Greyscale Regarding claim 6, Hatada discloses that four sides of the hexagon have a first length, and the remaining two sides have a second length different from the first length. Claim(s) 15 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over ‘547 in view of ‘744 as applied to claim 11 above, and further in view of Hatada. Regarding claim 15, ‘547 discloses that the device unit has a shape of hexagon in a top view, but does not disclose that the hexagon has a first side and a second side, wherein the first side has a greater length than the second side. Hatada discloses a similar device wherein the device unit has the shape of a hexagon with a first side having a greater length than the second side (Fig 2). Hatada discloses that such a configuration allows for a greater margin for error when contacts are disposed along a given direction (¶64). Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to use an elongated hexagon as disclosed by Hatada as the shape of the device unit in order to realize such a greater margin of error in contact formation. Regarding claim 18, ‘547 discloses that the device unit has a shape of hexagon in a top view, but does not disclose that the hexagon has four sides which have a first length, and the remaining two sides have a second length different from the first length. Hatada discloses a similar device wherein the device unit has the shape of a hexagon with four sides having a first length, and the remaining two sides having a second length different from the first length (Fig 2). Hatada discloses that such a configuration allows for a greater margin for error when contacts are disposed along a given direction (¶64). Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to use an elongated hexagon as disclosed by Hatada as the shape of the device unit in order to realize such a greater margin of error in contact formation. Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL P SHOOK whose telephone number is (571)270-7890. The examiner can normally be reached 9:00 am - 5:00 pm, Mon-Fri. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached at (571)272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL P SHOOK/Primary Examiner, Art Unit 2896
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Prosecution Timeline

Apr 18, 2024
Application Filed
Jul 23, 2026
Non-Final Rejection mailed — §103, §112
Sep 09, 2026
Response Filed
Sep 25, 2026
Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
96%
With Interview (+8.4%)
2y 0m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 653 resolved cases by this examiner. Grant probability derived from career allowance rate.

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