DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over [Peng et al (Fig. 3); 12,445,099] in view of [Pech (Fig. 1); 4,303,890].
Peng et al discloses an amplifier circuit comprising a first transistor (M2) and a second transistor (M3) configured as a first current mirror (M2 and M3) and wherein the first transistor (M2) has a first terminal (drain terminal of M2) and a second terminal (source terminal of M2) and a control terminal (gate terminal of M2) and wherein the second transistor (M3) has a first terminal (drain terminal of M3) and a second terminal (source terminal of M3) and a control terminal (gate terminal of M3), a first current source (BIAS) coupled between a supply node (the terminal receiving the supply voltage VCC2) and the first terminal (drain terminal of M2) of the first transistor (M2), a bias circuit output (V2) coupled to the second terminal (source terminal of M3) of the second transistor (M3), a first resistor (R1) coupled between the control terminal (gate terminal of M2) of the first transistor (M2) and the control terminal (gate terminal of M3) of the second transistor (M3), a capacitor (C1) coupled between the control terminal (gate terminal of M3) of the second transistor (M3) and a ground (ground), and a second current mirror (M4, M5) coupled to the first current mirror (M2 and M3) and the bias circuit output (V2). As described above, Peng et al discloses all the limitations in claim 16 except for that the capacitor being a variable capacitor. Pech discloses a current mirror circuit comprising a variable capacitor (15) which is coupled between the control terminal (base terminal of 18) of the second transistor (18) and a ground (ground). It would have been obvious to one of ordinary skill in the art at the time the invention was made would have found it obvious to have employed the variable capacitor at between the control terminal (gate terminal of M3 in Fig. 3 of Peng et al) of the second transistor (M3 in Fig. 3 of Peng et al) and a ground (ground in Fig. 3 of Peng et al) of Peng et al (Fig. 3), such as taught by Pech (Fig. 1) in order to provide the advantageous benefit of reducing the noisy signals of the current mirror circuit.
Claim(s) 16-20 and 30-33 are rejected under 35 U.S.C. 103 as being unpatentable over [Malchow (Fig. 1); 4,334,198] in view of [Pech (Fig. 1); 4,303,890].
Regarding claims 16 and 32, Malchow discloses an amplifier circuit comprising a first transistor (Q4) and a second transistor (Q1) configured as a first current mirror (Q4 and Q1) and wherein the first transistor (Q4) has a first terminal (Collector terminal of Q4) and a second terminal (emitter terminal of Q1) and a control terminal (base terminal of Q4) and wherein the second transistor (Q1) has a first terminal (collector terminal of Q1) and a second terminal (emitter terminal of Q1) and a control terminal (base terminal of Q1), a first current source (IS) coupled between a supply node (T2) and the first terminal (collector terminal of Q4) of the first transistor (Q4), a bias circuit output (the node between the transistors Q1 and Q5) coupled to the second terminal (emitter terminal of Q1) of the second transistor (Q1), a first resistor (R1) coupled between the control terminal (base terminal of Q4) of the first transistor (Q4) and the control terminal (base terminal of Q1) of the second transistor (Q1), a capacitor (C) coupled between the control terminal (base terminal of Q1) of the second transistor (Q1) and a ground (ground), and a second current mirror (Q3, Q5) coupled to the first current mirror (Q4 and Q1) and the bias circuit output (the node between the transistors Q1 and Q5). and an RF amplifier circuit (Q2) coupled to the bias circuit (Q4, Q1, Q3, Q5). As described above, Malchow discloses all the limitations in claim 1 except for that the capacitor being a variable capacitor. Pech discloses a current mirror circuit comprising a variable capacitor (15) which is coupled between the control terminal (base terminal of 18) of the second transistor (18) and a ground (ground). It would have been obvious to one of ordinary skill in the art at the time the invention was made would have found it obvious to have employed the variable capacitor at between the control terminal (base terminal of Q1 in Fig. 1 of Malchow) of the second transistor (Q1 in Fig. 1 of Malchow) and a ground (ground in Fig. 1 of Malchow) of Malchow (Fig. 1), such as taught by Pech (Fig. 1) in order to provide the advantageous benefit of reducing the noisy signals of the current mirror circuit.
Regarding claim 17, wherein the first transistor (Q4) and the second transistor (Q1) are bipolar transistors.
Regarding claim 18, Malchow in view of Pech further comprising a third transistor (Q3) configured as a diode connected transistor coupled between the second terminal (emitter terminal of Q4) of the first transistor (Q4) and the ground (ground in Fig. 1 of Malchow).
Regarding claim 19, wherein the third transistor (Q3) is a bipolar transistor.
Regarding claim 20, Malchow in view of Pech further comprising a fourth transistor (Q5) with a first terminal (collector terminal of Q5) coupled to the bias circuit output (the node between the transistors Q1 and Q5), a second terminal (emitter terminal of Q5) coupled to the ground (ground), and a control terminal (base terminal of Q5) coupled to a control terminal (base terminal of Q3) of the third transistor (Q3) and wherein the third transistor (Q3) and the fourth transistor (Q5) are configured as the second current mirror (Q3 and Q5).
Regarding claim 30, the current source (IS) is functionally equivalent to the claimed first current source.
Regarding claim 31, the first variable capacitor (15) is functionally equivalent to the claimed first variable capacitor.
Regarding claim 33, wherein the RF amplifier circuit (Q2) comprises a common emitter transistor and the bias circuit output (the node between the transistors Q1 and Q5) is coupled to a base (base terminal of Q2) of the common emitter transistor (Q2), and the RF amplifier output (the signal generating from the collector terminal of the transistor Q2) is coupled to a collector (collector terminal of the transistor Q2) of the common emitter transistor (Q2).
Claim(s) 34 is rejected under 35 U.S.C. 103 as being unpatentable over [Malchow (Fig. 1); 4,334,198] in view of [Pech (Fig. 1); 4,303,890] in further view of [TANAKA et al (Fig. 10); 2020/0,195,210].
Malchow in view of Pech discloses all the limitations in claim 34 except for that the common base transistor in a cascode configuration with the common emitter transistor, and wherein the RF amplifier output is coupled to a collector of the common base transistor. TANAKA et al discloses an amplifier circuit comprising a common base transistor (112) in a cascode configuration with the common emitter transistor (111), and wherein the RF amplifier output (RF3) is coupled to a collector (collector of the transistor 112) of the common base transistor (112). It would have been obvious to substitute TANAKA et al’s cascode amplifier (111 and 112 in Fig. 10 of TANAKA et al) in place of Malchow’s amplifier circuit (Q2 in Fig. 1 of Malchow) since Malchoe discloses a generic amplifier circuit thereby suggesting that any equivalent amplifier circuit would have been usable in Malchow’s reference.
Allowable Subject Matter
Claims 21-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance: Regarding claims 21 and 22, the closest prior art of record, Malchow does not disclose the following limitation: a second variable capacitor coupled between the first terminal of the second transistor and the second terminal of the second transistor. Regarding claim 23, the closest prior art of record, Malchow does not disclose the following limitation: a second current source coupled between the supply node and the second current mirror and the second current mirror comprises a fourth transistor and a fifth transistor.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
7,259,615 teaches a bias circuit with the current mirror circuits.
2015/0,061,771 also teaches a bias circuit with the current mirror circuits.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (571)272-1760. The examiner can normally be reached MONDAY-FRIDAY 5AM-11:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HENRY CHOE/ Primary Examiner, Art Unit 2843
#2985
Prosecution Insights