Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a switchable current mirror and a digital-to-analog converter” of claim 28 and “switchable capacitor network” of claim 29 must be shown or the features canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 26 and 29 are objected to because of the following informalities:
In claim 26, lines 5-6, “the second terminal of the fourth transistor is coupled to the first terminal of the fourth transistor.” should read as -- the first terminal of the second transistor --.
In claim 29, line 2, “capacitors consisting of of a varactor” should read as -- capacitors consisting of a varactor --.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 23-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 23, lines 4-7 recites the limitation “the fifth transistor includes a first terminal coupled to the bias circuit output, a second terminal coupled to the ground, and a control terminal; and the sixth transistor includes a first terminal coupled to the bias circuit output, a second terminal coupled to the ground, and a control terminal.”. It is unclear how both the fifth and sixth transistors of the second current mirror are connected to the bias circuit output through each first terminal. Therefore, the claim has an indefinite scope.
Claims 24-27 are rejected due to their dependency on the rejected claim 23.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16, 19, 23, 24, 30, 31, and 33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SUKEMORI (US 20210126600 A1) cited by the applicant, hereafter referred to as “SUKEMORI”.
Regarding claims 16, 19, 23, 24, 30, 31, and 33 in the embodiment of Fig. 1, SUKEMORI discloses:
A bias circuit (Fig. 1, bias circuits 20 and 30) for a radio frequency (RF) amplifier (amplifiers 10 and 11 receiving RF input signal RFin), the bias circuit comprising:
a first transistor (transistor Q12) and a second transistor (transistor Q11) configured as a first current mirror (as shown in Fig. 1), wherein the first transistor has a first terminal (Q12 collector), a second terminal (Q12 emitter), and a control terminal (Q12 base), and wherein the second transistor has a first terminal (Q11 collector), a second terminal (Q11 emitter), and a control terminal (Q11 base), wherein the first transistor and the second transistor are bipolar transistors (as shown in Fig. 1, per claim 19);
a first current source (bias control signal IB1, variable current source generates bias control signal IB1 per paragraph [0034] lines 6-9) arranged between a supply node (terminal 71 of Fig. 2 can be considered a common node connected through bias control 70) and the first terminal of the first transistor (Q12 collector);
a bias circuit output (node between R1 and R12) coupled to the second terminal of the second transistor (Q11 emitter, as shown in Fig. 1);
a second current mirror (Fig. 7A, transistor Q23 and Q24 of bias circuit 30 is analogous to bias circuit 30 of Fig. 1 per paragraph [0074]) coupled to the first current mirror and the bias circuit output (as shown in Fig. 1, bias circuit 30 is connected to node between R1 and R12); and
a second current source (bias control signal IB2, is connected to a variable current source per paragraph [0042]) coupled between the supply node and the second current mirror (Fig. 7A, current mirror comprising Q23 and Q24), and a third transistor in a diode-connected configuration (Fig. 1, Q13 shows a diode-connected transistor) coupled between the second terminal of the first transistor and a ground (as shown in Fig. 1, ground is connected to node between Q23 and Q13), wherein the second current mirror includes a fifth transistor and a sixth transistor (Fig. 7A, Q24 and Q23);
the fifth transistor includes a first terminal coupled to the bias circuit output (Fig. 7A, Q24 collector connected to node between R1 and R12 of Fig. 1), a second terminal (Q24 or emitter) coupled to the ground, and a control terminal (as shown in Fig. 7A); and
the sixth transistor includes a first terminal (Fig. 7A, Q23 collector connected to node between R1 and R12 of Fig. 1), a second terminal coupled to the ground, and a control terminal (as shown in Fig. 7A, per claim 23), wherein the second current mirror further comprises a second resistor (Fig. 7A, resistor R22)) coupled between the first terminal of the fifth transistor and the bias circuit output (as shown in Fig. 7A, connected to the node between R1 and R12 of Fig. 1, per claim 24); and
the RF amplifier circuit comprises:
a common-emitter transistor (amplifier transistor Q1), wherein the bias circuit output is coupled to a base of the common-emitter transistor (as shown in Fig. 1, through resistor R1), and the RF amplifier output (external terminal 87, shown to be connected to RFout in Fig. 2) is coupled to a collector of the common-emitter transistor (Q1 collector) (per claim 31).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17, 18, 25, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over SUKEMORI (US 20210126600 A1) in view of Sasho (US 20050179484 A1) both cited by the applicant, hereafter referred to as “SUKEMORI” and “Sasho”, respectively.
Regarding claim 17, 18, 25, and 28 in the embodiment of Figs. 1 and 7A, SUKEMORI discloses:
the control terminal of the first transistor (Q12 base) and the control terminal of the a second transistor (Q11 base); and
a capacitor (bypass capacitor C11) coupled between the control terminal of the second transistor and the ground (as shown in Fig. 1); and
fifth and sixth transistors (Fig. 7A, per claim 25); and
the first current source and the second current source (bias control signal, IB1 and IB2, per paragraphs [0034] and [0042]).
However, SUKEMORI is silent in teaching a first resistor coupled between the control terminal of the first transistor and the control terminal of the a second transistor; and
the capacitor is a variable capacitor selected from a group consisting of a varactor and switchable capacitor network, and the fifth and sixth transistors are MOS transistors, wherein the first current source and the second current source are selected from a group of current sources consisting of a switchable current mirror and a digital-to-analog converter.
Sasho teaches:
a first resistor (Fig. 4, resistor R2) coupled between the control terminal of the first transistor and the control terminal of the a second transistor (as shown in Fig. 4 between TR3 and TR4).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the design of the current mirrors as taught in SUKEMORI (Fig. 1) to further include a resistor as taught by Sasho (Fig. 4), to prevent oscillation (paragraph [0059], lines 6-8), thereby suggesting the obviousness of such a combination. It would further have been obvious to one having ordinary skill in the art to replace the capacitor as taught by SUKEMORI (Fig. 1) to be a variable capacitor to adjust capacitance, as it is known in the art, thereby suggesting the obviousness of such a modification. It would be further have been obvious for the fifth and sixth transistors to be MOS transistors as it is known in the art to replace bipolar transistors with similar transistors as taught by SUKEMORI (paragraph [0084], bias circuit 30 may be implement by metal metal-insulator-semiconductor (MIS) field-effect transistor, a metal-semiconductor (MES) field-effect transistor, or the like). It would also be further obvious first the first current source and the second current source are selected from a group of current sources consisting of a switchable current mirror and a digital-to-analog converter, in order to switch between the first and second bias circuit, as it is also suggested in SUKEMORI (paragraph [0009] lines 15-20), thereby suggesting the obviousness of such a combination.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over SUKEMORI (US 20210126600 A1) and Sasho (US 20050179484 A1) in further view of CHO (US 20080238553 A1) each cited by the applicant, hereafter referred to as “SUKEMORI”, “Sasho”, and “CHO”, respectively.
Regarding claim 29, SUKEMORI and Sasho, teaches:
the second capacitor (Sasho, Fig. 4, capacitor C2).
However, SUKEMORI and Sasho are silent in teaching, a group of capacitors consisting of a varactor and switchable capacitor network.
Cho teaches the group of capacitors consisting a varactor (Fig. 2, varactor diode 31).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to replace capacitor as taught in SUKEMORI (Fig. 1) with a varactor as taught by CHO (Fig. 2, varactor diode 31), to vary resistance and capacitance (paragraph [0058]), thereby suggesting the obviousness of such a combination.
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over SUKEMORI (US 20210126600 A1) cited by the applicant, in view of Fung (US 20120139642 A1), hereafter referred to as “SUKEMORI” and “Fung”, respectively.
Regarding claim 32, in the embodiment of Fig. 1, SUKEMORI discloses:
the RF amplifier circuit includes a common-emitter transistor (amplifier transistor Q1), wherein the bias circuit output is coupled to a base of the common-emitter transistor (as shown in Fig. 1, through resistor R1).
However, SUKEMORI is silent in teaching the RF amplifier further includes a common-base transistor in a cascode configuration with the common-emitter transistor, wherein the RF amplifier output is coupled to a collector of the common-base transistor.
Fung, in the embodiment of Fig. 1, teaches:
the RF amplifier further includes a common-base transistor (common emitter-connected transistor 14) in a cascode configuration with the common-emitter transistor (cascode transistor 16 is connected in cascode with common emitter-connected transistor 14), wherein the RF amplifier output is coupled to a collector (transistor 16 collector) of the common-base transistor (as shown in Fig. 1).
Accordingly, It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to replace RF amplifier as taught in SUKEMORI (Fig. 1) with the cascode RF amplifier configuration as taught by Fung (Fig. 1), to overcomes the difficulties of operating at this high current inflection point (paragraph [0035]), thereby suggesting the obviousness of such a combination.
Allowable Subject Matter
Claims 20, 21, 22 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 26 and 27 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 20, 21, 22, 26, and 27:
the cited prior art of record, SUKEMORI (US 20210126600 A1) cited by the applicant, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, “the fourth transistor is a bipolar transistor” per claim 20, “the first variable capacitor is coupled between the first terminal of the second transistor and the second terminal of the second transistor; the control terminal of the fourth transistor is coupled to the supply node; the first terminal of the fourth transistor is coupled to the supply node” per claims 21, 22, 26, and 27.
Claims 34 is allowed.
The following is an examiner’s statement of reasons for allowance:
Although the closest prior art of record, SUKEMORI (US 20210126600 A1) cited by the applicant, teaches most of the limitations of independent claim 34, the art alone or in combination does not teach that
“a first variable capacitor coupled between the first terminal of the second transistor and the second terminal of the second transistor; and a fourth transistor having a control terminal, a first terminal coupled to the supply node, and a second terminal coupled to the first terminal of the second transistor”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Malane Lieng/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
Prosecution Insights