DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 01/23/2026, in which claim 1 was amended, claims 2-3 were cancelled, has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application JP2018012427 filed on 01/29/2018. The foreign application is not in English. The certified copy of the foreign priority application JP2018012427 has been received.
Filing Dates for the Claims — All Claims Not Entitled to Priority Date
To be entitled to the filing date of the foreign priority application JP2018012427 that is not in English, an English translation of the non-English language foreign application JP2018012427 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, claim 1 recites the limitation “wherein an impurity concentration of the second semiconductor layer, which is sandwiched between the first semiconductor layer and the third semiconductor layer, overlaps the entirety of the gate electrode in the trench, and is not reached by the trench, is higher than each of an impurity concentration of the first semiconductor layer and an impurity concentration of the third semiconductor layer.” The long limitation is confusing. It is unclear from the above limitation which previously recited feature “overlaps the entirety of the gate electrode in the trench, and is not reached by the trench”: an impurity concentration of the second semiconductor layer, the second semiconductor layer, the first semiconductor layer or the third semiconductor layer.
For the purpose of this Action, the above limitation will be interpreted and examined as --wherein the second semiconductor layer is sandwiched between the first semiconductor layer and the third semiconductor layer, overlaps the entirety of the gate electrode in the trench, and is not reached by the trench; and wherein an impurity concentration of the second semiconductor layer is higher than each of an impurity concentration of the first semiconductor layer and an impurity concentration of the third semiconductor layer--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Masuda (US Pub. 20150236148) in view of Niimura et al. (US Pub. 20180158899) and Fujihira (US Pat. 6683347).
Regarding claim 1, Masuda discloses in Fig. 16-Fig. 26 a manufacturing method of a semiconductor device, comprising:
preparing a semiconductor substrate [11] comprising silicon and carbon;
forming a first semiconductor layer [12a] of a first conductivity type [n-type] over an upper surface of the semiconductor substrate [11][Fig. 16, paragraph [0105]];
forming, in the first semiconductor layer [12a], a first impurity region [18 right] and a second impurity region [18 left] of a second conductivity type [p-type] opposite to the first conductivity type [n-type], each of an entirety of an upper surface of the first impurity region [18 right] and an entirety of an upper surface of the second impurity region [18 left] is flush with an entirety of the upper surface of the first semiconductor layer [12a] while each of a bottom surface of the first impurity region [18 right] and a bottom surface of the second impurity region [18 left] is spaced apart from the bottom surface of the first semiconductor layer [12a][Fig. 16, paragraph [0106]];
forming a third semiconductor layer [12b] of the first conductivity type [n-type] over the first semiconductor layer [12a], the first impurity region [18 right], and the second impurity region [18 left] such that a bottom surface of the third semiconductor layer [12b] is in contact with each of the upper surface of the first semiconductor layer [12a], the upper surface of the first impurity region [18 right], and the upper surface of the second impurity region [18 left][Fig. 17, paragraph [0107]];
forming a third impurity region [14 and 16] of the second conductivity type [p-type] in the third semiconductor layer [12b][Fig. 18, paragraph [0108]];
forming a fourth impurity region [15] of the first conductivity type [n-type] in the third impurity region [14 and 16];
forming a trench [17] which penetrates through the fourth impurity region [15] and the third impurity region [14 and 16] and reaches the third semiconductor layer [12b][Fig. 21, paragraph [0110]-[0114]];
forming a gate insulating film [20] in the trench [17][Fig. 22, paragraph [0117]]; and
forming a gate electrode [30] so as to fill the trench [17] with the gate insulating film [20] interposed between the gate electrode [30] and an inner surface of the trench [17] [Fig. 24, paragraph [0120]].
Masuda fails to disclose
forming a second semiconductor layer of the first conductivity type in the first semiconductor layer such that an entirety of an upper surface of the second semiconductor layer is flush with the entirety of the upper surface of the first semiconductor layer while a bottom surface of the second semiconductor layer is spaced apart from a bottom surface of the first semiconductor layer;
i) the second semiconductor layer is interposed between the first impurity region and the second impurity region without the second semiconductor layer directly contacting the first impurity region or the second impurity region in plan view,
ii) the first semiconductor layer is interposed between the second semiconductor layer and the first impurity region in plan view, and
iii) the first semiconductor layer is interposed between the second semiconductor layer and the second impurity region in plan view;
iv) each of the entirety of the upper surface of the first impurity region and the entirety of the upper surface of the second impurity region is flush with the entirety of the upper surface of the second semiconductor layer;
forming the third semiconductor layer over the second semiconductor layer such that the bottom surface of the third semiconductor layer is in contact with the upper surface of the second semiconductor layer;
forming the trench without reaching the second semiconductor layer;
wherein in plan view, the second semiconductor layer is formed to overlap an entirety of the gate electrode and extends beyond a perimeter of the gate electrode;
wherein the second semiconductor layer is sandwiched between the first semiconductor layer and the third semiconductor layer, overlaps the entirety of the gate electrode in the trench, and is not reached by the trench; and
wherein an impurity concentration of the second semiconductor layer is higher than each of an impurity concentration of the first semiconductor layer and an impurity concentration of the third semiconductor layer.
Nimura et al. discloses in Figs. 8-9, Fig. 13
forming a second semiconductor layer [23a] of the first conductivity type [n type] in the first semiconductor layer [23a] such that an entirety of an upper surface of the second semiconductor layer [23a] is flush with the entirety of the upper surface of the first semiconductor layer [21a] while a bottom surface of the second semiconductor layer [23a] is spaced apart from a bottom surface of the first semiconductor layer [21a][Fig. 8, paragraph [0075]];
i) the second semiconductor layer [23a] is interposed between the first impurity region [22a] and the second impurity region [another 22a] without the second semiconductor layer [23a] directly contacting the first impurity region [22a] or the second impurity region [another 22a] in plan view [Fig. 8, paragraph [0075]];
ii) the first semiconductor layer [21a] is interposed between the second semiconductor layer [23a] and the first impurity region [22a] in plan view [Fig. 8], and
iii) the first semiconductor layer [21a] is interposed between the second semiconductor layer [23a] and the second impurity region [ another 22a] in plan view [Fig. 8];
iv) each of the entirety of the upper surface of the first impurity region [22a] and the entirety of the upper surface of the second impurity region [another 22a] is flush with the entirety of the upper surface of the second semiconductor layer [23a][Fig. 8];
forming the third semiconductor layer [21b-21f] over the second semiconductor layer [23a] such that the bottom surface [bottom surface of 21b] of the third semiconductor layer [21b-21f] is in contact with each of the upper surface of the first semiconductor layer [21a], the upper surface of the second semiconductor layer [23a], the upper surface of the first impurity region [22a], and the upper surface of the second impurity region [another 22a][Fig. 9, paragraph [0080]];
forming the trench without reaching the second semiconductor layer [21a][Fig. 13];
wherein in plan view, the second semiconductor layer [23a] is formed to overlap an entirety of the gate electrode [65] and extends beyond a perimeter of the gate electrode [65][Fig. 13, paragraph 0083]];
wherein the second semiconductor layer [23a] is sandwiched between the first semiconductor layer [21a] and the third semiconductor layer [21b-21f], overlaps the entirety of the gate electrode [65] in the trench, and is not reached by the trench [Fig. 9, Fig. 13]; and
wherein an impurity concentration of the second semiconductor layer [23a] is higher than each of an impurity concentration of the first semiconductor layer [21b] and an impurity concentration of the third semiconductor layer [21b-21f][paragraph [0075], paragraph [0080]].
For further support, Fujihira is cited.
Fujihira discloses in Fig. 4d, Fig. 5a, Fig. 12, Fig. 13, Fig. 14
forming a second semiconductor layer [6 or 32b or 52b] of the first conductivity type [n type] in the first semiconductor layer [first 32a or 52a] such that an entirety of an upper surface of the second semiconductor layer [6 or 32b or 52b] is flush with the entirety of the upper surface of the first semiconductor layer [32a or 52a] while a bottom surface of the second semiconductor layer [6 or 32b or 52b] is spaced apart from a bottom surface of the first semiconductor layer [32a or 52a][Fig. 4d, Fig. 5a, Fig. 14, column 9, lines 10-49];
i) the second semiconductor layer [6 or 32b or 42b] is interposed between the first impurity region [3 or 32c or 42c] and the second impurity region [another 3 or 32c or 42c] without the second semiconductor layer [6 or 32b or 42b] directly contacting the first impurity region [3 or 32c or 42c] or the second impurity region [another 3 or 32c or 42c] in plan view [Fig. 4d, Fig. 12, Fig. 13, column 9, lines 10-49];
ii) the first semiconductor layer [32a or 42a] is interposed between the second semiconductor layer [6 or 32b or 42b] and the first impurity region [3 or 32c or 42c] in plan view [Fig. 4d, Fig. 12, Fig. 13, column 9, lines 10-49], and
iii) the first semiconductor layer [32a or 42a] is interposed between the second semiconductor layer [6 or 32b or 42b] and the second impurity region [another 3 or 32c or 42c] in plan view [Fig. 4d, Fig. 12, Fig. 13, column 9, lines 10-49];
iv) each of the entirety of the upper surface of the first impurity region [3 or 32c or 42c] and the entirety of the upper surface of the second impurity region [another 3 or 32c or 42c] is flush with the entirety of the upper surface of the second semiconductor layer [6 or 42b] [Fig. 4d, Fig. 5a, Fig. 13, Fig. 14];
forming the third semiconductor layer [additional layer 32a or 42a or 52a] over the second semiconductor layer [6 or 32b or 42b or 52b] such that the bottom surface of the third semiconductor layer [additional layer 32a or 42a or 52a] is in contact with each of the upper surface of the first semiconductor layer [32a], the upper surface of the second semiconductor layer [6 or 32b or 42b or 52b], the upper surface of the first impurity region [3 or 32c or 42c or 52c], and the upper surface of the second impurity region [another 3 or 32c or 42c or 52c][Fig. 4d, Fig. 5a, Fig. 13, Fig. 14];
forming the trench without reaching the second semiconductor layer [52b][Fig. 14];
wherein in plan view, the second semiconductor layer [52b] is formed to overlap an entirety of the gate electrode [56] and extends beyond a perimeter of the gate electrode [56][Fig. 14];
wherein the second semiconductor layer [52b] is sandwiched between the first semiconductor layer [52a] and the third semiconductor layer [additional layer 52a], overlaps the entirety of the gate electrode [56] in the trench, and is not reached by the trench [Fig. 14]; and
wherein an impurity concentration of the second semiconductor layer [52b] is higher than each of an impurity concentration of the first semiconductor layer [52a] and an impurity concentration of the third semiconductor layer [additional layer 52a][column 9, lines 10-49, column 12, lines 64-67].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Nimura et al. and Fujihira into the method of Masuda to include forming a second semiconductor layer of the first conductivity type in the first semiconductor layer such that an entirety of an upper surface of the second semiconductor layer is flush with the entirety of the upper surface of the first semiconductor layer while a bottom surface of the second semiconductor layer is spaced apart from a bottom surface of the first semiconductor layer; i) the second semiconductor layer is interposed between the first impurity region and the second impurity region without the second semiconductor layer directly contacting the first impurity region or the second impurity region in plan view, ii) the first semiconductor layer is interposed between the second semiconductor layer and the first impurity region in plan view, and iii) the first semiconductor layer is interposed between the second semiconductor layer and the second impurity region in plan view; iv) each of the entirety of the upper surface of the first impurity region and the entirety of the upper surface of the second impurity region is flush with the entirety of the upper surface of the second semiconductor layer; forming the third semiconductor layer over the second semiconductor layer such that the bottom surface of the third semiconductor layer is in contact with the upper surface of the second semiconductor layer; forming the trench without reaching the second semiconductor layer; wherein in plan view, the second semiconductor layer is formed to overlap an entirety of the gate electrode and extends beyond a perimeter of the gate electrode; wherein the second semiconductor layer is sandwiched between the first semiconductor layer and the third semiconductor layer, overlaps the entirety of the gate electrode in the trench, and is not reached by the trench; and wherein an impurity concentration of the second semiconductor layer is higher than each of an impurity concentration of the first semiconductor layer and an impurity concentration of the third semiconductor layer. The ordinary artisan would have been motivated to modify Masuda in the above manner for the purpose of reducing the on-resistance and improving the tradeoff relation between the on-resistance and the breakdown voltage; improve reliability, improve avalanche resistance and reverse recovery resistance [column 13, lines 5-12 of Fujihira, paragraph [0085] of Nimura et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893