DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 6-7 and 16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 06/12/2026.
It is argued that Applicant submits that if any of the elected claims is found to be allowable, claims dependent therefrom should similarly be considered allowable in the same application.
As such, if any of the elected claims is found to be allowable, claims dependent therefrom should similarly be considered allowable in the same application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-15 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al. 20230217646.
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Regarding claim 1, figs. 12-13 of Lim discloses a semiconductor memory device comprising:
a semiconductor substrate 10;
a device isolation pattern 120 in the semiconductor substrate and defining an active pattern ACT extending in a first direction D4;
a bit line BL crossing the active pattern on the semiconductor substrate and extending in a second direction D1 forming an acute angle with the first direction;
a word line WL extending across the active pattern in a third direction D2 intersecting the second direction and extending into the semiconductor substrate (par [0055]);
a plurality of electrode plates 530 vertically stacked on the bit line;
a common electrode pattern BE extending through the plurality of electrode plates to the active pattern (LP in fig. 1, and in applicant’s drawing EP extends to CAC) on one side of the bit line; and
a ferroelectric pattern DL (par [0029]) between the common electrode pattern and the plurality of electrode plates,
wherein the bit line is in contact (there is an indirect contact) with an upper surface of the active pattern and an upper surface of the device isolation pattern.
Regarding claim 13, figs. 12-13 of Lim discloses a semiconductor memory device comprising:
a semiconductor substrate 10; an active pattern ACT in the semiconductor substrate and comprising a center portion and an edge portion extending from the center portion in a first direction (D4 – see fig. 12);
a device isolation pattern 120 in the semiconductor substrate and defining the active pattern;
a bit line BL comprising a metal pattern 330 and a metal barrier pattern 331, the bit line crossing the active pattern in a second direction D2 forming an acute angle with the first direction D4 on the semiconductor substrate;
a word line WL extending across the active pattern in a third direction intersecting the second direction and at least partially extending into the semiconductor substrate (par [0055]);
a first interlayer insulating layer 350 covering the bit line on the semiconductor substrate;
a plurality of electrode plates TE vertically stacked on the bit line;
a common electrode pattern BE extending through the plurality of electrode plates to the active pattern on one side of the bit line;
a ferroelectric pattern DL between the common electrode pattern and the plurality of electrode plates;
a capacitor contact LP extending through the first interlayer insulating layer on the active pattern, and between the common electrode pattern BE and the edge portion of the active pattern; and
a second interlayer insulating layer (TS,MS, BS) covering the plurality of electrode plates on the first interlayer insulating layer, wherein the metal barrier pattern of the bit line is in contact (indirectly) with an upper surface of the active pattern and an upper surface of the device isolation pattern.
Regarding claim 19, figs. 12-13 of Lim discloses a semiconductor memory device comprising:
a semiconductor substrate 10;
active patterns comprising a center portion and an edge portion extending from the center portion in a first direction;
a device isolation pattern in the semiconductor substrate and defining the active patterns;
a bit line extending across the active patterns on the semiconductor substrate in a second direction forming an acute angle with the first direction;
a word line extending across at least one of the active patterns in a third direction intersecting the second direction and at least partially extending into the semiconductor substrate;
a first interlayer insulating layer covering the bit line on the semiconductor substrate;
a plurality of electrode plates vertically stacked on the bit line and extending in the third direction;
a pair of common electrode patterns (see fig. 13) extending through the plurality of electrode plates to the active patterns, and adjacent to each other in the first direction;
ferroelectric patterns between the plurality of electrode plates and the pair of common electrode patterns;
capacitor contacts LPs extending through the first interlayer insulating layer on the active patterns, and between the pair of common electrode patterns and the edge portion of the active patterns; and
a second interlayer insulating layer (TS,MS, BS) covering the plurality of electrode plates on the first interlayer insulating layer, wherein the bit line is in contact (indirectly) with an upper surface of the active patterns and an upper surface of the device isolation pattern.
Regarding claim 2, fig. 13 of Lim discloses wherein the bit line comprises a metal pattern and a metal barrier pattern, and wherein the metal barrier pattern of the bit line is in contact with the upper surface of the active pattern.
Regarding claim 3, fig. 12 of Lim discloses wherein the active pattern comprises a center portion and an edge portion extending from the center portion in the first direction, and wherein the bit line is in contact (indirectly) with the center portion of the active pattern.
Regarding claim 4, fig. 13 of Lim discloses further comprising: a first interlayer insulating layer 350 covering the bit line on the semiconductor substrate; and a capacitor contact LP extending into the first interlayer insulating layer, and between the common electrode pattern and the edge portion of the active pattern.
Regarding claims 5 and 18, par [0063] and fig. 13 of Lim discloses further comprising: first 321 and second 325 spacers on sidewalls of the bit line on the semiconductor substrate; and an air gap AG between the first and second spacers.
Regarding claim 8, fig. 13 of Lim discloses wherein the plurality of electrode plates extend in the third direction.
Regarding claims 9 and 17, fig. 13 of Lim discloses wherein the plurality of electrode plates form a stepped structure at end portions thereof in the third direction, and wherein the plurality of electrode plates are connected to contact plugs TS at the end portions thereof in the third direction.
Regarding claim 10, fig. 13 of Lim discloses wherein the ferroelectric pattern comprises a plurality of ferroelectric layers.
Regarding claims 11, 14 and 20, par [0029] of Lim disclose wherein the ferroelectric pattern comprises hafnium oxide and at least one of zirconium (Zr), silicon (Si), aluminum (Al), yttrium (Y), gadolinium (Gd), lanthanum (La), scandium (Sc), and strontium (Sr).
Regarding claims 12 and 15, Lim discloses wherein the active pattern comprises a single crystal or polycrystalline semiconductor material, a two-dimensional semiconductor material, or an oxide semiconductor material.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
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