DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 04/18/2024 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 7-13, 15, 16, 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morimoto et al. U.S. Patent Application 2020/0233441 (hereinafter “Morimoto”) and further in view of Shah et al. U.S. Patent Application 2023/0170882 (hereinafter “Shah”).
Regarding claim 1, Morimoto teaches power switching circuitry (i.e. intelligent power device 34)(fig.2) comprising: a power switch (i.e. FET Q2)(fig.2) having a first terminal (refer to drain terminal of FET Q2)(fig.2) coupled to a first power domain (refer to junction 35 and power supply 1a)(fig.2) and having a second terminal (refer to source terminal of FET Q2)(fig.2) coupled to a second power domain (refer to power supply 1b)(fig.2); a diode (i.e. diode D2)(fig.2) coupled between the first and second terminals of the power switch (implicit); however, Morimoto does not teach a pull-down circuit coupled between the second terminal of the power switch and a gate terminal of the power switch. However, Shah teaches a pull-down circuit (i.e. switch device M2 124)(fig.1) coupled between the second terminal of the power switch and a gate terminal of the power switch (implicit)(refer to power switch 102)(fig.2). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power switching circuitry of Morimoto to include the pull-down circuit of Shah to provide the advantage of preventing false turn-on of the power switch (refer to Shah abstract).
Regarding claim 2, Morimoto and Shah teach the power switching circuitry of claim 1, further comprising: a passive electrical component (i.e. Shah capacitor C1 120)(fig.1) having a first terminal coupled to the first terminal of the power switch (refer to Shah drain of power switch 102)(fig.1) and having a second terminal coupled to the pull-down circuit (refer to Shah source of power switch 102)(fig.1).
Regarding claim 8, Morimoto and Shah teach the power switching circuitry of claim 1, wherein the power switch comprises an n-type transistor (refer to Morimoto [0040]) having a first source-drain terminal coupled to the first power domain (refer to Morimoto drain terminal of FET Q2)(fig.2) and having a second source-drain terminal coupled to the second power domain (refer to Morimoto source terminal of FET Q2)(fig.2).
Regarding claim 9, Morimoto and Shah teach the power switching circuitry of claim 1, wherein the pull-down circuit comprises an n-type transistor (implicit)(refer to Shah switch device M2 124)(fig.1) having a first source-drain terminal coupled to the second terminal of the power switch (refer to Shah source terminal of switch device M2 124)(fig.1) and having a second source-drain terminal coupled to the gate terminal of the power switch (refer to Shah drain terminal of switch device M2 124)(fig.1).
Regarding claim 10, Morimoto and Shah teach the power switching circuitry of claim 1, wherein the power switch comprises a first n-type transistor (refer to Morimoto [0040])(refer also to Shah power switch M0 102)(fig.1) having a first voltage rating (inherent), and wherein the pull-down circuit comprises a second n-type transistor (refer to Shah switch device M2 124)(fig.1) having a second voltage rating (inherent); however, Morimoto and Shah do not teach the second voltage rating different than the first voltage rating. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have the second voltage rating different than the first voltage rating, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power switching circuitry of Morimoto and Shah to include the second voltage rating different than the first voltage rating to provide the advantage of using a smaller transistor for the pull-down circuit since it does not need to handle as high of a voltage as the power switch, thereby making the overall circuit smaller.
Regarding claim 11, Morimoto and Shah teach the power switching circuitry of claim 10; however, they do not teach wherein the first voltage rating of the first n-type transistor is greater than the second voltage rating of the second n-type transistor. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the first voltage rating of the first n-type transistor is greater than the second voltage rating of the second n-type transistor, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power switching circuitry of Morimoto and Shah to include wherein the first voltage rating of the first n-type transistor is greater than the second voltage rating of the second n-type transistor to provide the advantage of using a smaller transistor for the pull-down circuit since it does not need to handle as high of a voltage as the power switch, thereby making the overall circuit smaller.
Regarding claim 12, Morimoto and Shah teach the power switching circuitry of claim 1, wherein the power switch comprises a first n-type transistor (refer to Morimoto [0040])(refer also to Shah power switch M0 102)(fig.1) having a first breakdown voltage (inherent), and wherein the pull-down circuit comprises a second n-type transistor (refer to Shah switch device M2 124)(fig.1) having a second breakdown voltage (inherent); however, Morimoto and Shah do not teach the second breakdown voltage less than the first breakdown voltage. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have the second breakdown voltage less than the first breakdown voltage, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power switching circuitry of Morimoto and Shah to have the second breakdown voltage less than the first breakdown voltage to provide the advantage of using a smaller transistor for the pull-down circuit since it does not need to handle as high of a voltage as the power switch, thereby making the overall circuit smaller.
Regarding claim 13, Morimoto and Shah teach the power switching circuitry of claim 1, wherein the power switch comprises a first n-type transistor (refer to Morimoto [0040])(refer also to Shah power switch M0 102)(fig.1) and wherein the pull-down circuit comprises a second n-type transistor (refer to Shah switch device M2 124)(fig.1); however, Morimoto and Shah do not teach the second n-type transistor smaller than the first n-type transistor. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have the second n-type transistor smaller than the first n-type transistor, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power switching circuitry of Morimoto and Shah to have the second n-type transistor smaller than the first n-type transistor to provide the advantage of using a smaller transistor for the pull-down circuit since it does not need to handle as high of a voltage as the power switch, thereby making the overall circuit smaller.
Regarding claim 15, Morimoto teaches circuitry (i.e. intelligent power device 34)(fig.2) comprising: a power switch (i.e. FET Q2)(fig.2) having a first terminal coupled (refer to drain terminal of FET Q2)(fig.2) to a first power supply terminal (refer to junction 35 and power supply 1a)(fig.2) and having a second terminal (refer to source terminal of FET Q2)(fig.2) coupled to a second power supply terminal (refer to power supply 1b)(fig.2), the power switch having a first voltage rating (inherent); a diode (i.e. diode D2)(fig.2) having an anode terminal coupled to the second terminal of the power switch (implicit)(refer to fig.2) and having a cathode terminal coupled to the first terminal of the power switch (implicit)(refer to fig.2); however, Morimoto does not teach a pull-down transistor having a first source-drain terminal coupled to the second terminal of the power switch and having a second source-drain terminal coupled to a gate terminal of the power switch, the pull-down transistor having a second voltage rating different than the first voltage rating. However, Shah teaches a pull-down transistor (i.e. switch device M2 124)(fig.1) having a first source-drain terminal coupled to the second terminal of the power switch (implicit)(refer to source of switch device M2 124 and source of power switch 102)(fig.1) and having a second source-drain terminal coupled to a gate terminal of the power switch (implicit)(refer to drain of switch device M2 124 and gate of power switch 102)(fig.1); the pull-down transistor having a second voltage rating (inherent). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuitry of Morimoto to include the pull-down transistor of Shah to provide the advantage of preventing false turn-on of the power switch (refer to Shah abstract). However, Morimoto and Shah do not teach the second voltage rating different than the first voltage rating. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have the second voltage rating different than the first voltage rating, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuitry of Morimoto and Shah to include the second voltage rating different than the first voltage rating to provide the advantage of using a smaller transistor for the pull-down transistor since it does not need to handle as high of a voltage as the power switch, thereby making the overall circuit smaller.
Regarding claim 16, Morimoto and Shah teach the circuitry of claim 15; however, they do not teach wherein the second voltage rating of the pull-down transistor is less than the first voltage rating of the power switch. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the second voltage rating of the pull-down transistor is less than the first voltage rating of the power switch, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuitry of Morimoto and Shah to include wherein the second voltage rating of the pull-down transistor is less than the first voltage rating of the power switch to provide the advantage of using a smaller transistor for the pull-down transistor since it does not need to handle as high of a voltage as the power switch, thereby making the overall circuit smaller.
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morimoto and Shah as applied to claim 2 above, and further in view of Ohura et al. U.S. Patent No. 5,818,281 (hereinafter “Ohura”).
Regarding claim 3, Morimoto and Shah teach the power switching circuitry of claim 2, further comprising: a voltage clamping circuit (i.e. Shah voltage clamp 118)(fig.1) coupled to the pull-down circuit (implicit); however, Morimoto and Shah do not teach a current discharge circuit configured to sink current flowing through the voltage clamping circuit. However, Ohura teaches a current discharge circuit (refer to Ohura switch 12 and current source 14)(fig.2) configured to sink current flowing through the voltage clamping circuit (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power switching circuitry of Morimoto and Shah to include the current discharge circuit of Ohura to provide the advantage of discharging the charge built up in the pull-down circuit to ensure the pull-down circuit turns off, thereby better protecting against nuisance operation of the power switch (refer to Ohura col. 3 lines 36-46)
Regarding claim 4, Morimoto, Shah, and Ohura teach the power switching circuitry of claim 3, further comprising: a clamp disabling circuit (i.e. Shah disable clamp 126)(fig.1) configured to selectively disable the voltage clamping circuit (implicit).
Claim(s) 7, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morimoto and Shah as applied to claims 2 and 15 above, and further in view of Doyle et al. U.S. Patent No. 5,717,560 (hereinafter “Doyle”).
Regarding claim 7, Morimoto and Shah teach the power switching circuitry of claim 2; however, they do not teach wherein the passive electrical component comprises a resistor. However, Doyle teaches wherein the passive electrical component comprises a resistor (i.e. resistor 317)(fig.3). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power switching circuitry of Morimoto and Shah to include the resistor of Doyle to provide the advantage of reducing the sensitivity of the circuit to the time scale of the ESD event, thereby fixing the gate to a voltage in a much more controllable manner (refer to Doyle col. 2 lines 3-11).
Regarding claim 18, Morimoto and Shah teach the circuitry of claim 15; however, they do not teach the circuitry further comprising a feedforward resistor having a first terminal coupled to the first terminal of the power switch and having a second terminal coupled to a gate terminal of the pull-down transistor. However, Doyle teaches the circuitry further comprising a feedforward resistor (i.e. resistor 317)(fig.3) having a first terminal coupled to the first terminal of the power switch (implicit)(refer to n-channel transistor 303)(fig.3) and having a second terminal coupled to a gate terminal of the pull-down transistor (implicit)(refer to n-channel transistor 315)(fig.3). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuitry of Morimoto and Shah to include the resistor of Doyle to provide the advantage of reducing the sensitivity of the circuit to the time scale of the ESD event, thereby fixing the gate to a voltage in a much more controllable manner (refer to Doyle col. 2 lines 3-11).
Regarding claim 19, Morimoto, Shah, and Doyle teach the circuitry of claim 18, further comprising: a voltage clamping circuit (i.e. Shah voltage clamp 118)(fig.1) configured to limit a voltage at the gate terminal of the pull-down transistor (implicit); and an additional transistor (i.e. Shah disable clamp 126)(fig.1)(refer also to Shah disable clamp device M3 126)(fig.2) configured to selectively disable the voltage clamping circuit (implicit).
Claim(s) 14 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morimoto and Shah as applied to claims 1 or 15 above, and further in view of Ohhinata et al. U.S. Patent No. 4,039,865 (hereinafter “Ohhinata”).
Regarding claim 14, Morimoto and Shah teach the power switching circuitry of claim 1; however, they do not teach the power switching circuitry further comprising a resistor having a first terminal coupled to the second terminal of the power switch and having a second terminal coupled to the gate terminal of the power switch. However, Ohhinata teaches the power switching circuitry further comprising a resistor (i.e. resistor R1)(fig.3) having a first terminal coupled to the second terminal of the power switch (refer to terminal K)(fig.3) and having a second terminal coupled to the gate terminal of the power switch (refer to terminal Gk)(fig.3). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the power switching circuitry of Morimoto and Shah to include the resistor of Ohhinata to provide the advantage of preventing erroneous operation of the power switch due to small transients (refer Ohhinata col. 2 line 65 to col. 3 line 5).
Regarding claim 17, Morimoto and Shah teach the circuitry of claim 15; however, they do not teach the circuitry further comprising a resistor having a first terminal coupled to the first source-drain terminal of the pull-down transistor and having a second terminal coupled to the second source-drain terminal of the pull down transistor. However, Ohhinata teaches the circuitry further comprising a resistor (i.e. resistor R1)(fig.3) a first terminal coupled to the first source-drain terminal of the pull-down transistor (refer to terminal K)(fig.3) and having a second terminal coupled to the second source-drain terminal of the pull down transistor (refer to terminal Gk)(fig.3). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuitry of Morimoto and Shah to include the resistor of Ohhinata to provide the advantage of preventing erroneous operation of the power switch due to small transients (refer Ohhinata col. 2 line 65 to col. 3 line 5).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morimoto and further in view of Doyle.
Regarding claim 20, Morimoto teaches circuitry (i.e. intelligent power device 34)(fig.2) comprising: a power transistor (i.e. FET Q2)(fig.2) having a first source-drain terminal (refer to drain terminal of FET Q2)(fig.2) electrically coupled to a first power domain (refer to junction 35 and power supply 1a)(fig.2) and having a second source-drain terminal (refer to source terminal of FET Q2)(fig.2) electrically coupled to a second power domain (refer to power supply 1b)(fig.2); a diode (i.e. diode D2)(fig.2) having a cathode terminal coupled to the first source-drain terminal of the power transistor (implicit)(refer to fig.2) and having an anode terminal coupled to the second source-drain terminal of the power transistor (implicit)(refer to fig.2); however, Morimoto does not teach a pull-down transistor having a first source-drain terminal coupled to the second source-drain terminal of the power transistor and having a second source-drain terminal coupled to a gate terminal of the power transistor; and a resistor having a first terminal coupled to the first source-drain terminal of the power transistor and having a second terminal coupled to a gate terminal of the pull-down transistor. However, Doyle teaches a pull-down transistor (i.e. n-channel transistor 315)(fig.3) having a first source-drain terminal coupled to the second source-drain terminal of the power transistor (implicit)(refer to n-channel transistor 303)(fig.3) and having a second source-drain terminal coupled to a gate terminal of the power transistor (implicit)(refer to n-channel transistor 303)(fig.3); and a resistor (i.e. resistor 317)(fig.3) having a first terminal coupled to the first source-drain terminal of the power transistor (implicit)(refer to n-channel transistor 303)(fig.3) and having a second terminal coupled to a gate terminal of the pull-down transistor (implicit)(refer to n-channel transistor 315)(fig.3). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuitry of Morimoto to include the pull-down transistor and resistor of Doyle to provide the advantage of preventing false turn-on of the power switch (refer to Doyle col. 2 lines 3-11 and col. 4 lines 1-13).
Allowable Subject Matter
Claims 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claims 5 and 6 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 5, especially a gate driver circuit coupled to the second terminal of the power switch and having an output that is coupled to the clamp disabling circuit and the gate terminal of the power switch.
Conclusion
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838