DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/2/2025 has been entered.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the data writing” at the seventh-to-last line of the claim. There is insufficient antecedent basis for this limitation of the claim. This limitation has been interpreted as “[[the]] data writing.” The other independent claims have a similar issue. The dependent claims inherit this rejection. Appropriate correction is required.
REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-7, 9-11, 13-17, 19, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pletka et al (US 2024/0427515).
Regarding Claim 1, Pletka teaches a memory system, comprising:
a memory device (NAND flash memory system 150 of Fig. 1B) including a plurality of blocks, wherein a block includes a plurality of memory cells (Paragraph 0035); and
a memory controller coupled to the memory device (flash controller 140 of Fig. 1B) and configured to:
determine a storage mode for the block based on a total amount of valid data in all of the plurality of blocks (total data utilization, which is “the [total] amount of valid data stored [in all of the plurality of blocks] relative to the total usable capacity of the NAND flash memory system 150,” Paragraph 0046, is determined at step 604 of Fig. 6, and a result, storage modes for a given block is determined as SLC, at step 618, or QLC, at step 614 of Fig. 6), different storage modes based on a number of data bits stored in each memory cell in the block (Paragraph 0034, each mode such as SLC, QLC, etc is based on a number of bits stored in each cell) wherein the different storage modes comprise a first mode and a second mode; wherein in the first mode, the data bits stored in each memory cell of the block comprise one bit (“SLC pool 402 in which fully programmed blocks store only a single bit per cell,” Paragraph 0049); and in the second mode, the data bits stored in each memory cell of the block comprise multiple bits (“a QLC pool 400 in which fully programmed blocks store four bits per cell,” Paragraph 0049);
acquire the total amount of valid data in all of the plurality of blocks (total data utilization, which is “the amount of valid data stored relative to the total usable capacity of the NAND flash memory system 150,” Paragraph 0046, is determined at step 604 of Fig. 6);
calculate a ratio of the total amount of valid data to a total memory space of the plurality of blocks to obtain a proportion of valid data (total data utilization, which is “the amount of valid data stored relative to the total usable capacity of the NAND flash memory system 150,” Paragraph 0046, is determined at step 604 of Fig. 6);
and
determine, based on the proportion of valid data, the storage mode for a new block to be opened (a determination is made based on the proportion of valid data whether a new QLC block is to be opened at steps 606 and 614, or whether a new SLC block is to be opened at step 618 of Fig. 6)
configure a new block to perform the data writing with the first mode when the number of blocks adopting the first mode determined based on the proportion of valid data is greater than a current number of blocks actually adopting the first mode (step 618 of Fig. 6 a “ready-to-use”/new block is configured in SLC/first mode, Paragraphs 0066-0069); and
configure the new block to perform the data writing with the second mode when the number of blocks adopting the first mode determined based on the proportion of valid data is less than or equal to a current number of blocks actually adopting the first mode (a new QLC block is to be opened at steps 606 and 614 of Fig. 6, Paragraphs 0066-0069, and particularly “SLC stem blocks 500 can conveniently be drawn from those identified in queue 3 of RTU [new] queues 306a”).
Regarding Claim 3, the cited prior art teaches the memory system of Claim 1, wherein
the memory controller is configured to:
configure dynamically a number of blocks adopting the first mode when the proportion of valid data is greater than or equal to a first threshold (on Fig. 7, between first resizing thresholds 708 and second resizing threshold 710, the SLC blocks 700 are dynamically configured); and
stop configuring dynamically the number of blocks adopting the first mode when the proportion of valid data is greater than or equal to a second threshold (after resizing threshold 710, the SLC are stopped from being dynamically configured);
wherein the first threshold is less than the second threshold (shown on Fig. 7).
Regarding Claim 4, the cited prior art teaches the memory system of Claim 3, wherein the memory controller is configured to:
configure the number of blocks adopting the first mode to be a first number when the proportion of valid data is a first proportion (between 0 and first threshold 708 of Fig. 7, 100% of the blocks are SLC as shown according to curve 700, Paragraph 0068);
configure the number of blocks adopting the first mode to be a second number when the proportion of valid data is a second proportion (between first threshold 708 and second threshold 710 of Fig. 7, the blocks configured as SLC are configured as shown according to curve 700, Paragraph 0068);
and
configure the number of blocks adopting the first mode to be a third number when the proportion of valid data is a third proportion (beyond second threshold 710 of Fig. 7, the blocks configured as SLC are 0% as shown according to curve 700, Paragraph 0068);
wherein the first proportion is less than the second proportion, and the second proportion is less than the third proportion (shown on Fig. 7);
the first number is greater than the second number, and the second number is greater than the third number (shown on Fig. 7).
Regarding Claim 5, the cited prior art teaches the memory system of Claim 4, wherein the proportion of valid data is linearly correlated with the number of blocks adopting the first mode, both between the first proportion (between 0 and first threshold 708 of Fig. 7, 100% of the blocks are SLC as shown according to curve 700, which is linear, Paragraph 0068) and the second proportion and between the second proportion and the third proportion (between first threshold 708 and second threshold 710 of Fig. 7, there is shown at least two linear proportions, Paragraph 0068); and
a ratio of a difference between the second number and the first number to a difference between the second proportion and the first proportion is different from a ratio of a difference between the third number and the second number to a difference between the third proportion and the second proportion (shown on Fig. 7).
Regarding Claim 6, the cited prior art teaches the memory system of Claim 3, wherein the memory controller is configured to:
query a target mapping table using the proportion of valid data to determine the number of blocks adopting the first mode (the table represented by curve 700 of Fig. 7, Paragraph 0068, which correlates the proportion of valid data with the number of blocks adopting the first mode); the target mapping table includes a correspondence relationship between values of different proportions of valid data and corresponding numbers of blocks adopting the first mode (shown on Fig. 7).
Regarding Claim 7, the cited prior art teaches the memory system of Claim 6, wherein the memory controller is further configured to:
select the target mapping table from among a plurality of mapping tables before querying the target mapping table (Fig. 7 shows curves 700, 702, 704 and 706 all represent different mapping tables);
the correspondence relationship between the values of different proportions of valid data and the corresponding numbers of blocks adopting the first mode, contained in each of the plurality of mapping tables, is different from one another (shown on Fig. 7).
Regarding Claim 9, the cited prior art teaches the memory system of Claim 1, wherein a block comprises a plurality of pages; the memory controller is further configured to:
acquire a count of pages occupied by valid data in all of the plurality of blocks to obtain the total amount of valid data (total data utilization, which is “the amount of valid data stored relative to the total usable capacity of the NAND flash memory system 150,” Paragraph 0046, is determined, also see pages described on Paragraph 0002).
Regarding Claim 10, the cited prior art teaches the memory system of Claim 1, wherein the valid data includes data that has not been erased, indicated to be erased, updated or rewritten by a host system (see description of valid data on Paragraphs 0042-0043).
Claim 11 is the method corresponding to the memory system of claim 1, and is rejected under similar rationale.
Claim 13 is the method corresponding to the memory system of claim 3, and is rejected under similar rationale.
Claim 14 is the method corresponding to the memory system of claim 4, and is rejected under similar rationale.
Claim 15 is the method corresponding to the memory system of claim 5, and is rejected under similar rationale.
Claim 16 is the method corresponding to the memory system of claim 6, and is rejected under similar rationale.
Claim 17 is the method corresponding to the memory system of claim 7, and is rejected under similar rationale.
Claim 19 is the method corresponding to the memory system of claim 9, and is rejected under similar rationale.
Claim 20 is the non-transitory storage medium corresponding to the memory system of claim 1, and is rejected under similar rationale.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
On pages 9-10 of the submitted remarks, applicant argues the cited prior art fails to teach to “configure a new block to perform the data writing with the first mode when the number of blocks adopting the first mode determined based on the proportion of valid data is greater than a current number of blocks actually adopting the first mode” as recited in the independent claims because “Converting QLC to SLC when the number of SLC blocks is less the predetermined maximum number of SLC blocks is not configuring a new block to perform the data writing in SLC mode when the number of blocks adopting SLC based on the proportion of valid data is greater than a current number of blocks actually adopting SLC.”
This argument has been considered but is not persuasive.
At step 610 of Fig. 6, Pletka teaches to determine, based on the proportion of valid data, the storage mode for a new block to be opened, giving a “new block” the plain meaning of the art as an “erased block ready for data to be written.” If the number of blocks adopting the first mode determined based on the proportion of valid data is greater than a current number of blocks actually adopting the first mode, step 618 of Fig. 6 will be performed, where a “ready-to-use”/new block is configured in SLC/first mode, Paragraphs 0066-0069.
If the number of blocks adopting the first mode determined based on the proportion of valid data is less than or equal to a current number of blocks actually adopting the first mode, a new QLC block is to be opened at steps 606 and 614 of Fig. 6, Paragraphs 0066-0069, and particularly “SLC stem blocks 500 can conveniently be drawn from those identified in queue 3 of RTU [new] queues 306a” to be used as the new QLC block.
Therefore, the cited prior art teaches to “configure a new block to perform the data writing with the first mode when the number of blocks adopting the first mode determined based on the proportion of valid data is greater than a current number of blocks actually adopting the first mode” as recited in the independent claims.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Kurita et al (US 2022/0043604) teaches a MEMORY SYSTEM AND WRITE CONTROL METHOD.
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. ' 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1, 3-7, 9-11, 13-17, 19, and 20 have been rejected.
DIRECTION OF FUTURE CORRESPONDENCE
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Giardino whose telephone number is (571) 270-3565 and can normally be reached on M-F 9:00-5:00- 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Jared Rutz can be reached on (571) 272 - 5535. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
/MARK A GIARDINO JR/Primary Examiner, Art Unit 2135