Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 21-27 and 29-39 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gower et al., US PGPub 2009/0063729
With respect to claim 1, Gower teaches a control circuit, comprising:
an internal operation circuit configured to generate an internal command based on an access unit of a memory in a plurality of memories (pars 59-63, and fig. 5, memory hub controller 514 converts the read data command into an appropriate format for attached memory devices. This is based on matching the burst length to the width of the data channel, the burst length corresponding to the access unit); and
a storage circuit configured to store information regarding the access unit (par. 59, the configuration register storing how many beats of data should be sent on a read access),
wherein the access unit includes a burst length which is different with from another access unit (pars. 60-61, the burst length for a particular memory device, which may be a different burst length than other memory devices 506),
wherein the control circuit associates the memory with an error correction scheme of a host (pars. 63-64, the memory hub controller associates the memory with an ECC scheme), and
wherein the access unit indicates a size of data accessed by the memory at a time (pars. 59-60, a burst length is the size of data that can be accessed by the memory at a time).
With respect to claim 21, Gower teaches the control circuit of claim 1, wherein the internal operation circuit comprises:
an access unit comparison circuit configured to compare a size of data received from the host with the access unit of the memory (pars. 59-62, the memory hub controller 514 and burst logic 534 compare the burst size of the read command with the burst size of the memory devices); and
an internal command generation circuit configured to generate the internal command on a basis of comparison information (pars. 60-62, the internal read command is only for 16 bytes instead of the full burst of 64).
With respect to claim 22, Gower teaches the control circuit of claim 1, wherein the internal operation circuit comprises:
an access unit comparison circuit configured to compare a size of request data received from the host with the access unit of the memory (pars. 59-62, the memory hub controller 514 and burst logic 534 compare the burst size of the read command with the burst size of memory devices); and
an internal command generation circuit configured to generate the internal command on a basis of comparison information (pars. 60-62, the internal read command is only for 16 bytes instead of the full burst of 64).
With respect to claim 23, Gower teaches the control circuit of claim 21, wherein when the size of the received data is larger than the access unit based on the comparison information, the internal command generation circuit generates the internal command for performing a write operation with respect to one or more of the plurality of memories through a repetitive write operation of a plurality of times (par. 70, the write operation occurs across multiple beats).
With respect to claim 24, Gower teaches the control circuit of claim 21, wherein when the size of the data received from the host is less than or equal to the access unit based on the
comparison information, the internal command generation circuit generates the internal command for performing a one-time write operation with respect to one or more of the plurality of memories (pars. 66-67, when the write command is for less than the full burst, only the portion of the full burst is written, in the example, a quarter burst, or 16 bytes).
With respect to claim 25, Gower teaches the control circuit of claim 1, wherein the storage circuit stores error correction information on the data received from the host (pars. 72-73 and fig. 6, generating the error correction codes based on the data received at the memory hub device from memory controller 632, and writing the error code data to memory).
With respect to claim 26, Gower teaches the control circuit of claim 22, wherein when the size of the request data is larger than the access unit on the basis of the comparison information, the internal command generation circuit generates the internal command for performing a read operation from one or more of the plurality of memories through a repetitive read cycle of a plurality of times (pars. 58-59, performing the read in multiple beats).
With respect to claim 27, Gower teaches the control circuit of claim 22, wherein when the size of the data received from the host is less than or equal to the access unit on the basis of the comparison information, the internal command generation circuit generates the internal
command for performing a one-time read operation (pars. 60-62, the read for 16 bytes, the access unit in this example, is generated and performed).
With respect to claim 29, Gower teaches the control circuit of claim 1, further comprising:
an error correction circuit configured to generate error correction information on data
read from one or more of the plurality of memories (pars. 64-65 and fig. 5, memory device interface 510 reads the data and ECC information from memory, and generates the error correction information from the applicable bytes).
With respect to claim 30, Gower teaches the control circuit of claim 29, wherein the error correction circuit generates the error correction information on the data read from one or more of the plurality of memories pars. 64-65 and fig. 5, memory device interface 510 reads the data and ECC information from memory, and generates the error correction information from the applicable bytes).
With respect to claim 31, Gower teaches the control circuit of claim 29, wherein the error correction circuit performs error correction on the data read from one or more of the plurality of memories on a basis of a command from the host and performs an operation for writing the data in one or more of the plurality of memories again (par. 68, the ECC generation logic 634 generates the error correction data and writes the data).
With respect to claim 32, Gower teaches the control circuit of claim 1, wherein a signal is transmitted/received to/from the host and one or more of the plurality of memories in a protocol format (par. 46).
With respect to claim 33, Gower teaches a memory device comprising:
a control circuit configured to generate an internal command from a received command on a basis of data of a host, a unit of an error correction code, and an access unit of one or more of a plurality of memories in order to associate an error correction scheme of the host (pars 59-65, and fig. 5, memory hub device receives a read data command from the memory controller 532 over memory channel 508, the memory hub controller 514 converts the read data command into an appropriate format for attached memory devices 506. This is based on matching the burst length to the width of the data channel, the burst length corresponding to the access unit, and along with the error correction code); and
the one or more of the plurality of memories configured to operate based on the internal command received from the control circuit (par. 60, memory device 506 executes the read command),
wherein the access unit indicates a size of data accessed by the one or more of the
plurality of memories that the plurality of memories access at a time (par. 60, the burst length, in this example 16 bytes, corresponds to the size of data accessed by the memories at a time).
With respect to claim 34, Gower teaches the memory device of claim 33, wherein the host generates the received command and operates according to a preset error correction scheme (par. 60 and fig. 5, the memory hub device receives the read data command generated at memory controller 532, the host. Par. 64 discloses operating according to a preset error correction scheme).
With respect to claim 35, Gower teaches the memory device of claim 33, wherein one or more of the plurality of memories include an error correction logic (pars. 64-55, the error protection code used between the memories 506 and the memory hub device).
With respect to claim 36, Gower teaches the memory device of claim 33, wherein the control circuit further comprises:
an access unit comparison circuit configured to compare a size of data received from
the host with the access unit of one or more of the memories for a write operation and compare a size of request data received from the host with the access unit of one or more of the memories to generate comparison information in a read operation (pars. 59-62, the memory hub controller 514 and burst logic 534 compare the burst size of the read command with the burst size of the memory devices, and pars. 66-67, with respect to the write operation); and
an internal command generation circuit configured to generate the internal command on a basis of the comparison information (pars. 66-67, when the write command is for less than the full burst, only the portion of the full burst is written, in the example, a quarter burst, or 16 bytes, and pars. 60-62, the internal read command is only for 16 bytes instead of the full burst of 64).
With respect to claim 37, Gower teaches the memory device of claim 36, wherein the control circuit generates the internal command for writing the data and the error correction code through one or more number of times on a basis of a result obtained by comparing the access unit with the size of the received data (par. 70, the write operation occurs across multiple beats to write the full amount of data necessary, and par. 76 which describes writing the error correction code as part of the data transfer).
With respect to claim 38, Gower teaches the memory device of claim 35, wherein, when the received command instructs a read operation, the control circuit reads request data and the error correction code from one or more of the plurality of memories and transmits the request data and the error correction code to the host (pars. 64-65 and fig. 5, memory device interface 510 reads the data and ECC information from memory, for transmission to memory controller 532).
With respect to claim 39, Gower teaches the memory device of claim 38, wherein the control circuit generates the internal command for reading the data and the error correction code through one or more number of times on a basis of a result obtained by comparing the access unit with a size of the request data (pars. 58-59, performing the read in multiple beats).
Allowable Subject Matter
Claims 28 and 40-41 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: No prior art of record teaches transmitting a failure signal to the host when a request data requested from the host is not acquired within a preset time, in combination with all of the limitations of the respective parent claim.
Response to Arguments
Applicant’s arguments, see remarks, page 6, filed 12/18/2025, with respect to the rejection(s) of claim(s) 1 and 21-41 under 35 USC 112 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection of claims 1, 21-27 and 29-39 is made in view of 35 USC 102(a)(1) as being unpatentable over Gower et al., US PGPub 2009/0063729.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN DARE whose telephone number is (571)272-4069. The examiner can normally be reached M-F 9:00-5:00.
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/RYAN DARE/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132