Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/19/2026 has been entered.
Claims 1-20 are presented for Examination.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 12, 13, 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kolla et.al. (U.S Patent Application Publication 2017/0344102; hereinafter “Kolla”); in view of Zarei et.al. (U.S Patent 8,947,067; (Reference cited as prior art in previous office action)]
Regarding Claim 1 , Kolla discloses , A system-on-chip, comprising:
a functional circuit configured to receive a supply voltage and perform a processing operation; [“..adaptive voltage modulation circuit 100 that detects if a supply voltage (V) provided to a load circuit 102 falls below a droop threshold voltage (VDT) (i.e., detects a supply voltage droop)”, 0017; “FIG. 5 illustrates an example of a processor-based system 500 that can employ the adaptive voltage modulation circuits 100, 300, and 400 illustrated in FIGS. 1, 3, and 4, respectively. In this example, the processor-based system 500 includes one or more central processing units (CPUs) 502, “, 0046];
a voltage droop detection circuit configured to monitor the supply voltage and generate a detection signal indicating whether a voltage droop has occurred[ “a supply voltage droop detection and mitigation circuit 104 that includes a detection circuit 106 configured to generate a droop detection signal 108 in an active state in response to the supply voltage (V) being less than the droop threshold voltage (VDT).”, 0018];
a clock generation circuit configured to output a clock signal[ “root clock signal CLK_RT′ that is generated by a phase-locked loop (PLL) 322 “, 0031; Fig.3]; and
a clock modulation circuit[“The clock adjustment circuit 110 “, Fig.3] configured to receive the detection signal and the clock signal, generate an adaptive clock signal by modulating the clock signal to correspond to the detection signal, and provide the adaptive clock signal to the functional circuit[ “The clock adjustment circuit 110 also includes a second input node 324 that is electrically coupled to the output node 318 of the comparator circuit 106′ such that the second input node 324 receives the droop detection signal 108′. Further, the clock adjustment circuit 110 includes an output node 326 on which the clock adjustment circuit 110 is configured to provide the load clock signal CLK_LD′. As previously described above, adjusting the load clock signal CLK_LD′ in response to detecting a supply voltage droop can reduce or avoid timing failures caused by the supply voltage droop while other portions of the adaptive voltage modulation circuit 300 adjust the supply voltage (V) to reduce the occurrence of supply voltage droops.”, 0031; Fig.3], wherein the voltage droop detection circuit comprises:
a reference voltage generation circuit configured to generate the reference voltage[“ ..The digital threshold value (DV) is a digital representation of the droop threshold voltage (VDT′), wherein the droop threshold register 304 is configured to provide the digital threshold value (DV) on an output node 306 of the droop threshold register 304. Additionally, the supply voltage droop detection and mitigation circuit 302 includes a digital-to-analog converter (DAC) 308 to convert the digital threshold value (DV) into the droop threshold voltage (VDT′) used by the comparator circuit 106′. .. 0029; ( i.e the droop threshold voltage corresponds to the reference voltage) ]; and
a detection signal generation circuit configured to generate the detection signal by comparing the reference voltage with the supply voltage (VSUP) [ “the comparator circuit 106′ includes a first input node 314 electrically coupled to the output node 312 of the DAC 308 so as to receive the droop threshold voltage (VDT′), as well as a second input node 316 that receives the supply voltage (V). The comparator circuit 106′ also includes an output node 318 on which the comparator circuit 106′ is configured to provide the droop detection signal 108′. More specifically, the droop detection signal 108′ generated by the comparator circuit 106′ transitions to an active state in response to the droop threshold voltage (VDT′) being greater than the supply voltage (V). ..”, 0030] , and
wherein the reference voltage generation circuit is further configured to increase a level of the supply voltage based on determining that VSUP expected droop is higher than a predetermined value. [“the adaptive voltage modulation circuit 100 increases the supply voltage (V) in response to the load circuit 102 experiencing supply voltage droops for a higher percentage of the defined period (e.g., a higher throttle percentage)..”, 0023; “.. the droop detection signal 108′ is in an active state in response to detecting a supply voltage droop. .. “, 0030;” the adaptive voltage modulation circuit 300 also employs a supply voltage adjust circuit 328 that includes a counter circuit 114′ configured to count the number of cycles of the reference clock signal CLK_REF during which the supply voltage (V) is less than the droop threshold voltage (VDT′). .. ”, 0032; “, in order to adjust the supply voltage (V) based on the adjust-up and adjust-down counts UP_CNT, DN_CNT, the supply voltage adjust circuit 328 also includes an adjust-up register 338 and an adjust-down register 340. In particular, the adjust-up register 338 is configured to store an adjust-up threshold value (AU), while the adjust-down register 340 is configured to store an adjust-down threshold value (AD).. the adjust-up and adjust-down threshold values (AU), (AD) can be determined during testing of a corresponding chip and stored in the adjust-up and adjust-down registers 338, 340.”, 0034; “..the voltage adjust-up signal 118′ is initially in an inactive state, wherein the voltage adjust-up circuit 116′ generates the voltage adjust-up signal 118′ in an active state in response to the adjust-up count UP_CNT indicated by the up count signal 336(1) being greater than the adjust-up threshold value (AU) at any time during the defined period…”, 0035; “ the supply voltage controller circuit 124 is configured to increase the supply voltage (V) provided to the load circuit 102 in response to the voltage adjust-up signal 118′ being in an active state. Additionally, the supply voltage controller circuit 124 is configured to decrease the supply voltage (V) provided to the load circuit 102 in response to the voltage adjust-down signal 122′ being in an active state. “, 0037; ( i.e. increasing the supply voltage value based on the droop detection count higher than a predetermined / adjust-up threshold (i.e predetermined) value)].
However, Kolla does not expressly disclose a voltage droop detection control circuit configured to control a reference voltage to remain constant; wherein the voltage droop detection control circuit is further configured to adjust the reference voltage according to a process corner based on offsets between process corners.
In the same field of endeavor ( e.g. automatic calibration of bandgap voltage reference generator to reduce the effect of process variations on the bandgap voltage), Zarei teaches ,
a voltage droop detection control circuit configured to control a reference voltage to remain constant[ “..The automatic power control circuit shown in FIG. 1, for example, is an example of a circuit design 412 that may incorporate the bandgap voltage reference source 402.. “, col 5 lines 62-67; col 6 lines 1-19;” In operation op-amp 606 forces the voltage over the R.sub.ext (V.sub.R) to be the same as V.sub.D4, by changing the V.sub.bias. Basically, the output of op-amp 606 generates same current value for two identical current sources 620 and 622. V.sub.D4 is compared to a reference voltage (V.sub.REF), to sense the how much the diode-voltage is deviating from a constant reference voltage (V.sub.REF). The difference (V.sub.D4-V.sub.REF) is amplified by the amplifier-stage 612, and then compared to the constant reference voltages (e.g. V.sub.REF1, V.sub.REF2, V.sub.REF3, and V.sub.REF4) via several comparators 614-620. The outputs(e.g. S1, S2, S3, and S4) 502 of..”, col 7 lines 47-57; ( i.e controlling the reference voltage to remain constant)] ;
wherein the voltage droop detection control circuit is further configured to adjust the reference voltage according to a process corner based on offsets between process corners. [ “col 1 lines 45-54; “Referring to FIGS. 4A-4C, in accordance with principles of the present disclosure a bandgap voltage reference source 402 comprises a bandgap voltage generating section 404 and a calibration section 406. The bandgap voltage reference source 402 outputs a voltage level V.sub.BG. The details of this circuit will be discussed below. In some embodiments, the bandgap voltage reference source 402 may be incorporated as a component in a larger circuit design 412. The automatic power control circuit shown in FIG. 1, for example, is an example of a circuit design 412 that may incorporate the bandgap voltage reference source 402.. some circuits such as bandgap voltage references may need to be individually calibrated in order to compensate for resulting variations in device process corners.”, col 5 lines 62-67;; “ a bandgap voltage reference circuit, if the ratio of R2 to R1 is set for so-called "nominal" process corners, then chips whose devices have nominal process corners will behave as intended; in other words, their output voltage will vary within an acceptable range with changes in the ambient temperature. However, bandgap voltage reference circuits in chips that have fast or slow process corners, or any process corner other than a nominal process corner, may exhibit a wide swing in output voltage with changes in ambient temperature…”, col 4 lines 24-44; “ It is known that variations of a voltage V.sub.D4 (=V.sub.BE4) across the diode D4 over temperature is dependent on the actual value of V.sub.D4. ..Therefore, if the variations of V.sub.BE4 for each process corner are known, the required resistor ratio of (R.sub.2/R.sub.1), which depends on the .delta.V.sub.BE/.delta.T, can be found by generating a difference with a reference voltage (V.sub.REF). This difference is then amplified (V.sub.out) and then will be compared to several reference voltages using the comparators 614-620. ..col 8 lines 53-67; “..the comparators 614-620 would have to be able to detect voltage levels with resolution on the order of 0.03V. Such resolution imposes tight requirements for the comparators 614-620 in terms of offset voltage characteristics, and high accuracy for the reference voltages V.sub.REF1, V.sub.REF2, V.sub.REF3, and V.sub.REF4 supplied to the comparators…”, col 9 lines 1-17; Fig.7( i.e. the calibration circuit detects the reference voltage variations / droop and adjusts the reference voltage(V.sub.REF1, V.sub.REF2, V.sub.REF3, V.sub.REF4)according to offsets between different process corners)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kolla with Zarei. Zarei’s teaching of automatic calibration of voltage regulators to reduce the effect of process variations on the bandgap voltage will substantially improve Kolla’s system to provide an accurate voltage reference by compensating variations in device process corners.
Regarding Claim 12, Kim discloses, an operating method of a system-on-chip, the operating method comprising:
monitoring, by a voltage droop detection circuit included in the system-on-chip, a supply voltage, wherein the supply voltage is received by a functional circuit included in the system-on-chip, and the functional circuit is configured to perform a processing operation[“..adaptive voltage modulation circuit 100 that detects if a supply voltage (V) provided to a load circuit 102 falls below a droop threshold voltage (VDT) (i.e., detects a supply voltage droop)”, 0017; “FIG. 5 illustrates an example of a processor-based system 500 that can employ the adaptive voltage modulation circuits 100, 300, and 400 illustrated in FIGS. 1, 3, and 4, respectively. In this example, the processor-based system 500 includes one or more central processing units (CPUs) 502, “, 0046; “a supply voltage droop detection and mitigation circuit 104 that includes a detection circuit 106 configured to generate a droop detection signal 108 in an active state in response to the supply voltage (V) being less than the droop threshold voltage (VDT).”, 0018 ];
comparing a level of the supply voltage with a level of a reference voltage; generating a detection signal, based on a result of comparing the level of the supply voltage with the level of the reference voltage [[“ ..The digital threshold value (DV) is a digital representation of the droop threshold voltage (VDT′), wherein the droop threshold register 304 is configured to provide the digital threshold value (DV) on an output node 306 of the droop threshold register 304. Additionally, the supply voltage droop detection and mitigation circuit 302 includes a digital-to-analog converter (DAC) 308 to convert the digital threshold value (DV) into the droop threshold voltage (VDT′) used by the comparator circuit 106′. .. 0029; ( i.e the droop threshold voltage corresponds to the reference voltage) ; “the comparator circuit 106′ includes a first input node 314 electrically coupled to the output node 312 of the DAC 308 so as to receive the droop threshold voltage (VDT′), as well as a second input node 316 that receives the supply voltage (V). The comparator circuit 106′ also includes an output node 318 on which the comparator circuit 106′ is configured to provide the droop detection signal 108′. More specifically, the droop detection signal 108′ generated by the comparator circuit 106′ transitions to an active state in response to the droop threshold voltage (VDT′) being greater than the supply voltage (V). ..”, 0030]; and
adjusting a frequency of a clock signal, based on the detection signal [“ the clock adjustment circuit 110 can decrease a frequency of the load clock signal CLK_LD to be less than a frequency of a root clock signal CLK_RT received by the clock adjustment circuit 110 in response to the droop detection signal 108 transitioning to an active state (i.e., in response to detecting a supply voltage droop). “, 0018;” decreasing the frequency of the load clock signal CLK_LD reduces a frequency at which the load circuit 102 operates, which may reduce or avoid timing failures caused by the supply voltage droop. As a non-limiting example, the clock adjustment circuit 110 in this aspect decreases the frequency of the load clock signal CLK_LD by dividing the root clock signal CLK_RT. ..”, 0019; “The clock adjustment circuit 110 also includes a second input node 324 that is electrically coupled to the output node 318 of the comparator circuit 106′ such that the second input node 324 receives the droop detection signal 108′. .. 0031; Fig.3; ];
wherein the reference voltage generation circuit is further configured to increase a level of the supply voltage based on determining that VSUP expected droop is higher than a predetermined value. [“the adaptive voltage modulation circuit 100 increases the supply voltage (V) in response to the load circuit 102 experiencing supply voltage droops for a higher percentage of the defined period (e.g., a higher throttle percentage)..”, 0023; “.. the droop detection signal 108′ is in an active state in response to detecting a supply voltage droop. .. “, 0030;” the adaptive voltage modulation circuit 300 also employs a supply voltage adjust circuit 328 that includes a counter circuit 114′ configured to count the number of cycles of the reference clock signal CLK_REF during which the supply voltage (V) is less than the droop threshold voltage (VDT′). .. ”, 0032; “, in order to adjust the supply voltage (V) based on the adjust-up and adjust-down counts UP_CNT, DN_CNT, the supply voltage adjust circuit 328 also includes an adjust-up register 338 and an adjust-down register 340. In particular, the adjust-up register 338 is configured to store an adjust-up threshold value (AU), while the adjust-down register 340 is configured to store an adjust-down threshold value (AD).. the adjust-up and adjust-down threshold values (AU), (AD) can be determined during testing of a corresponding chip and stored in the adjust-up and adjust-down registers 338, 340.”, 0034; “..the voltage adjust-up signal 118′ is initially in an inactive state, wherein the voltage adjust-up circuit 116′ generates the voltage adjust-up signal 118′ in an active state in response to the adjust-up count UP_CNT indicated by the up count signal 336(1) being greater than the adjust-up threshold value (AU) at any time during the defined period…”, 0035; “ the supply voltage controller circuit 124 is configured to increase the supply voltage (V) provided to the load circuit 102 in response to the voltage adjust-up signal 118′ being in an active state. Additionally, the supply voltage controller circuit 124 is configured to decrease the supply voltage (V) provided to the load circuit 102 in response to the voltage adjust-down signal 122′ being in an active state. “, 0037; ( i.e. increasing the supply voltage value based on the droop detection count higher than a predetermined / adjust-up threshold (i.e predetermined) value)].
However, Kolla does not expressly disclose wherein the reference voltage is adjusted according to a process corner based on offsets between process corners.
In the same field of endeavor ( e.g. automatic calibration of bandgap voltage reference generator to reduce the effect of process variations on the bandgap voltage), Zarei teaches ,
wherein the reference voltage is adjusted according to a process corner based on offsets between process corners [ “col 1 lines 45-54; “Referring to FIGS. 4A-4C, in accordance with principles of the present disclosure a bandgap voltage reference source 402 comprises a bandgap voltage generating section 404 and a calibration section 406. The bandgap voltage reference source 402 outputs a voltage level V.sub.BG. The details of this circuit will be discussed below. In some embodiments, the bandgap voltage reference source 402 may be incorporated as a component in a larger circuit design 412. The automatic power control circuit shown in FIG. 1, for example, is an example of a circuit design 412 that may incorporate the bandgap voltage reference source 402.. some circuits such as bandgap voltage references may need to be individually calibrated in order to compensate for resulting variations in device process corners.”, col 5 lines 62-67; col 6 lines 1-19;” In operation op-amp 606 forces the voltage over the R.sub.ext (V.sub.R) to be the same as V.sub.D4, by changing the V.sub.bias. Basically, the output of op-amp 606 generates same current value for two identical current sources 620 and 622. V.sub.D4 is compared to a reference voltage (V.sub.REF), to sense the how much the diode-voltage is deviating from a constant reference voltage (V.sub.REF). The difference (V.sub.D4-V.sub.REF) is amplified by the amplifier-stage 612, and then compared to the constant reference voltages (e.g. V.sub.REF1, V.sub.REF2, V.sub.REF3, and V.sub.REF4) via several comparators 614-620. The outputs(e.g. S1, S2, S3, and S4) 502 of..”, col 7 lines 47-57; “ a bandgap voltage reference circuit, if the ratio of R2 to R1 is set for so-called "nominal" process corners, then chips whose devices have nominal process corners will behave as intended; in other words, their output voltage will vary within an acceptable range with changes in the ambient temperature. However, bandgap voltage reference circuits in chips that have fast or slow process corners, or any process corner other than a nominal process corner, may exhibit a wide swing in output voltage with changes in ambient temperature…”, col 4 lines 24-44; “ It is known that variations of a voltage V.sub.D4 (=V.sub.BE4) across the diode D4 over temperature is dependent on the actual value of V.sub.D4. ..Therefore, if the variations of V.sub.BE4 for each process corner are known, the required resistor ratio of (R.sub.2/R.sub.1), which depends on the .delta.V.sub.BE/.delta.T, can be found by generating a difference with a reference voltage (V.sub.REF). This difference is then amplified (V.sub.out) and then will be compared to several reference voltages using the comparators 614-620. ..col 8 lines 53-67; “..the comparators 614-620 would have to be able to detect voltage levels with resolution on the order of 0.03V. Such resolution imposes tight requirements for the comparators 614-620 in terms of offset voltage characteristics, and high accuracy for the reference voltages V.sub.REF1, V.sub.REF2, V.sub.REF3, and V.sub.REF4 supplied to the comparators…”, col 9 lines 1-17; Fig.7( i.e. the calibration circuit detects the reference voltage variations / droop and adjusts the reference voltage(V.sub.REF1, V.sub.REF2, V.sub.REF3, V.sub.REF4)according to offsets between different process corners)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kolla with Zarei. Zarei’s teaching of automatic calibration of voltage regulators to reduce the effect of process variations on the bandgap voltage will substantially improve Kolla’s system to provide an accurate voltage reference by compensating variations in device process corners.
Regarding Claim 13, Kolla discloses, wherein the detection signal is a signal indicating whether a voltage droop of the supply voltage has occurred, and the detection signal is generated when the level of the supply voltage is less than the level of the reference voltage[0030].
Regarding Claim 14, Kolla discloses , wherein adjusting the frequency of the clock signal comprises: adjusting the frequency of the clock signal and outputting an adaptive clock signal, when the level of the supply voltage is less than the level of the reference voltage[ 0018-0019;0031].
Claims 2-10, 15, 16, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kolla in view of Zarei as applied to claims 1,12 further in view of Kim et.al. (U.S Patent Application Publication 2020/0089299; hereinafter “Kim”; (Reference cited as prior art in previous office action)
Regarding claims 2, 15, Kolla , Zarei discloses the limitations outlined in claims 1, 12.
However, Kolla , Zarei does not expressly disclose a first frequency divider configured to divide a frequency of the clock signal and output a first divided clock signal, a second frequency divider configured to divide the frequency of the clock signal and output a second divided clock signal and a multiplexer configured to select and provide any one of the first divided clock signal and the second divided clock signal to the functional circuit, in response to the detection signal.
In the same field of endeavor (e.g. A voltage droop monitoring circuit includes a counter configured to generate a count value based on the selected oscillation signal, and a droop detector configured detect droop in the power supply voltage of a functional circuit block based on the count value and at least one threshold value) Kim discloses, wherein the clock modulation circuit comprises:
a first frequency divider configured to divide a frequency of the clock signal and output a first divided clock signal[“Referring to FIG. 3B, a clock modulation circuit 120a may include a plurality of frequency dividers 121, 122, 123 and 124, a multiplexer 125a and a signal generator 126a”, 0063; “The frequency dividers 121, 122, 123 and 124 receive the clock signal CLK, divide the clock signal CLK with different division ratios and generate division clock signals DCLK1, DCLK2, DCLK3 and DCLK4 which have different frequencies”, 0065; Fig.3B]
a second frequency divider configured to divide the frequency of the clock signal and output a second divided clock signal[0065; Fig.3B]and
a multiplexer configured to select and provide any one of the first divided clock signal and the second divided clock signal to the functional circuit, in response to the detection signal [ “The signal generator 126a receives the first error signal ERR1, generates a selection signal SS1 corresponding to the first error signal ERR1 and provides the selection signal SS1 to the multiplexer 125a.”, 0064;” The multiplexer 125a selects one of the division clock signals DCLK1, DCLK2, DCLK3 and DCLK4 in response to the selection signal SS1 and outputs the selected one as the adaptive clock signal ACLK..”, 0066].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim with Kolla in view of Zarei. Kim’s teaching of a voltage droop monitoring circuit including a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals will substantially improve Kolla in view of Zarei’s system to select a clock signal for the corresponding error/ droop with the supply voltage by implementing a plurality of frequency dividers and multiplexers to select an adaptive clock signal corresponding to the droop/ non-droop state.
Regarding Claim 3, Kim discloses, wherein the multiplexer is further configured to output any one of the first divided clock signal and the second divided clock signal as the adaptive clock signal 0066].
Regarding claims 4, 16, Kim discloses, wherein a frequency of the first divided clock signal is less than a frequency of the clock signal, and a frequency of the second divided clock signal is about equal to the frequency of the clock signal [ “… A frequency of the division clock signal DCLK1 may be the same as the frequency of the clock signal CLK, each frequency of the division clock signals DCLK2, DCLK3 and DCLK4 may be smaller than the frequency of the clock signal CLK…”, 0065].
Regarding Claim 5, Kim discloses, wherein, when the detection signal indicates that the voltage droop of the supply voltage has been detected, the multiplexer outputs and provides the adaptive clock signal to the functional circuit.
Regarding Claim 6, Kim discloses, wherein, when the detection signal indicates that the voltage droop of the supply voltage has not been detected, the multiplexer provides the clock signal to the functional circuit [ “..a selection signal SS1 having one or more second selection values over time are output if the input error signal ERR indicates an end of droop. By providing several selection options (e.g., dividers) during manufacture, a desired divider option for a droop state and a desired divider option or options over time for a non-droop may be set based on empirical study of the SoC 10 post manufacture”,0066; “And, the signal generator 126a is configured to change the selection signal SS1 periodically, in response to the error signal ERR1 indicating no droop, such that different dividers are selected and the ratio of the two clocks ACLK/CLK increases each time (e.g., ⅔, ¾, ⅘, 1) until the adaptive clock signal ACLK returns to a pre-droop or non-droop state (e.g., equals the clock signal CLK (e.g., is divided by 1)). While not shown in FIG. 3B, the clock signal CLK may also be directly supplied to the multiplexer 125a as an input. “, 0115 ].
Regarding claims 7, 8, 9, 17, Kim discloses and generate a sensing signal indicating a temperature state of the system-on-chip[ “”The SoC 10 includes a functional circuit 110 operating based on a power supply voltage VDD and a voltage droop monitoring circuit 200 including a plurality of ring oscillators and monitoring the power supply voltage VDD. In the method, the plurality of ring oscillators 320a˜320k generate a plurality of oscillation signals OS1˜OSk robust to a change of temperature, based on the power supply voltage VDD (S210).”, 0190; 0061].
wherein the clock modulation circuit is further configured to output any one of the clock signal and the adaptive clock signal[0065;0115], based on the sensing signal [0061] [ Claim 8]
wherein the clock modulation circuit is further configured to output the adaptive clock signal when the temperature inside the system-on-chip exceeds a reference temperature[0061; 0190; ( i.e detecting the change in temperature)].[ Claim 9]
However, Kim does not expressly disclose a temperature sensor configured to sense a temperature inside the system-on-chip, exceeding a reference temperature.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kim to disclose a temperature sensor configured to sense a temperature inside the system-on-chip , exceeding a reference temperature as Kim teaches detecting change in operating environment of the system-on-chip with respect to temperature and voltage changes and providing an adaptive clock signal based on the error signal to control the droop in the supply voltage and enhance performance of the system.
Regarding Claim 10, Kim discloses, wherein the voltage droop detection circuit is arranged adjacent to the functional circuit inside the system-on-chip[ 0131-0132; Fig.10].
Claim 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Zarei further in view of Kolla et.al. (U.S Patent Application Publication 2017/0344102; hereinafter “Kolla”)
Regarding Claim 18, Kim discloses, A system-on-chip, comprising:
a first functional circuit configured to receive a supply voltage and perform a first processing operation [0174“..The PMIC 800 may provide the first power supply voltage VDD1 to the CPU 710 “, 0176; 0188; Fig.16];
a first voltage droop detection circuit configured to monitor the supply voltage and generate a first detection signal indicating whether a voltage droop has occurred [ “The voltage droop monitoring circuit 200 may receive the power supply voltage VDD through the power line PL, may monitor a level of the power supply voltage VDD and may provide the clock modulation circuit 120 with an error signal ERR if a droop occurs in the power supply voltage VDD. ..”, 0044; “The level detector 211 compares the level of the power supply voltage VDD with the reference voltage VREF and may output a detection signal DS with a first logic (high) level if the level of the power supply voltage VDD is lower than the reference voltage VREF.”, 0058; Fig.1; Fig.2 B];
a second functional circuit configured to receive the supply voltage and perform a second processing operation[ “the memory control interface 760 may output a command to the memory device 850 according to a request from the CPU 710. The memory control interface 760 may write data in the memory device 850 or read data from the memory device 850 based on operation of the application processor 700…”, 0175; 0188 “… a third power supply voltage VDD3 to the memory device 850…”, 0176; Fig.17; (i.e the memory control interface with the memory device corresponds to the second functional circuit)]; 0058;
monitor the supply voltage and generate a second detection signal indicating whether the voltage droop has occurred [ 0058; Fig.1; Fig.2B (i.e. the level detector outputs a detection signal based on comparison with power supply voltage level and the reference voltage supplied by the functional circuits ) ; “..The comparator 254 outputs the second error signal ERR2 including a plurality of bits indicating difference between the counting value CV and at least one of the threshold values RTH1˜RTHt. That is, the second error signal ERR2 may indicates a degree of droop of the power supply voltage VDD. The signal generator 126b in the clock modulation circuit 120b of FIG. 3C generates the selections signal SS2 in response to the second error signal ERR2, and thus the clock modulation circuit 120b may output the adaptive clock signal ACLK which has a frequency depending on the degree of the droop (voltage droop)”, 0106 ( i.e generating a second error signal based on the degree of the voltage droop. Therefore, detecting a second droop and generating a second detection signal)]
a clock generation circuit configured to output a clock signal [ “The clock generator 730 may generate a clock signal CLK to provide the clock signal CLK to the clock modulation circuit 720.”, 0178]; and
a clock modulation circuit configured to receive the first and second detection signals and the clock signal, generate a first adaptive clock signal and a second adaptive clock signal by modulating the clock signal to correspond to the first and second detection signals, respectively, and provide the first adaptive clock signal and the second adaptive clock signal to the first functional circuit and the second functional circuit, respectively[ “ the clock modulation circuit 720 may generate a first adaptive clock signal ACLK1 and a second adaptive clock signal ACLK2 based on the clock signal CLK, may provide the first adaptive clock signal ACLK1 to the CPU 710 and may provide the second adaptive clock signal ACLK2 to the memory control interface 760”, 0179;” the functional circuit 110 may provide the voltage droop monitoring circuit 200 with a status signal STS indicating operating status (e.g., temperature, operating voltage, change in operating voltage, etc.) and operating speed of the functional circuit 110. The functional circuit 110, or other circuitry external or internal to the voltage drop monitoring circuit 200, may supply a reference voltage VREF. The reference voltage VREF may be generated according to any dynamic voltage frequency scale (DVFS) technique, which may also affect the operating voltage level VDD scheme “, 0044; “The signal generator 126b in the clock modulation circuit 120b of FIG. 3C generates the selections signal SS2 in response to the second error signal ERR2, and thus the clock modulation circuit 120b may output the adaptive clock signal ACLK which has a frequency depending on the degree of the droop (voltage droop)”, 0106; (i.e generating a respective clock adaptive signal to the corresponding functional circuits based on the error / detection signals)].
wherein the first voltage droop detection circuit comprises:
a first control circuit configured to control a first reference voltage to remain constant[ “The controller 210 receives the power supply voltage VDD, a reference voltage VREF and the status signal STS and may generate the first through third control signals CTL1, CTL2 and CTL3 based on the level of the power supply voltage VDD…”, 0055; Fig.2A; “ In FIG. 8, VREF denotes a reference voltage provided to the controller 210, LTH denotes a first threshold value, UNTH denotes a second threshold value and RO count value denotes the counting value of the counter 230.”, 0108; “if the droop occurs in the power supply voltage VDD, a frequency of the clock signal CLK needs to be adjusted quickly, and the adaptive clock signal ACLK is provided from the clock modulation circuit 120 by dividing or multiplexing the clock signal CLK in the clock modulation circuit 120..”, 0112; ( i.e as illustrated in Fig.8 the VREF remains constant , the controller modulates the clock to adjust the supply voltage according to the reference voltage by controlling the reference voltage to remain constant) ];
a first reference voltage generation circuit configured to generate the first reference voltage[“The functional circuit 110, or other circuitry external or internal to the voltage drop monitoring circuit 200, may supply a reference voltage VREF. The reference voltage VREF may be generated according to any dynamic voltage frequency scale (DVFS) technique, which may also affect the operating voltage level VDD scheme.”, 0048]; and
a first detection signal generation circuit configured to generate the first detection signal by comparing the first reference voltage with the supply voltage[ “The level detector 211 compares the level of the power supply voltage VDD with the reference voltage VREF and may output a detection signal DS with a first logic (high) level if the level of the power supply voltage VDD is lower than the reference voltage VREF.”, 0058],
control a second reference voltage to remain constant [0055; Fig.2A; “ In FIG. 8, VREF denotes a reference voltage provided to the controller 210, ...”, 0108; 0112; ( i.e as illustrated in Fig.8 the VREF remains constant , the controller modulates the clock to adjust the supply voltage according to the reference voltage generated by the respective functional circuits . Hence controlling the respective reference voltage to remain constant)]
generate the second reference voltage[ 0048; i.e. each functional circuit provides a reference voltage and provides status signals based on their respective operating conditions. Therefore, the respective functional circuits corresponds to the reference voltage generator)]
generate the second detection signal by comparing the second reference voltage with the supply voltage to [0048; (i.e. The power supply voltage level is adjusted according to the reference voltage obtained from the functional circuits and generates respective detection signal ); 106; ( i.e generating a second error signal based on the degree of the voltage droop. Therefore, detecting a second droop and generating a second detection signal)] .
However, Kim does not expressly disclose a second voltage droop detection circuit and the second voltage droop detection circuit comprises a second control circuit, a second reference voltage generation circuit and a second detection signal generation circuit. Specifically, Kim discloses detecting droop in the power supply voltage with respect to the operating status and reference voltage supplied by the respective functional blocks The clock modulation circuit provides an adaptive clock signal to the respective functional blocks based on their corresponding error/ detection signal . Further teaches a controller to provide the detection signal based on the voltage level droop of the functional circuits with respect to the reference voltage.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Kim to implement a second voltage droop detection circuit and the second voltage droop detection circuit comprises a second control circuit, a second reference voltage generation circuit and a second detection signal generation circuit, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co.V.Bemis Co.,193 USPQ 8.
However, Kim does not expressly disclose a first control circuit configured to control a first reference voltage to remain constant; control a second reference voltage to remain constant ; wherein the first control circuit is further configured to adjust the first reference voltage according to a process corner based on offsets between process corners, and wherein the second control circuit is further configured to adjust the second reference voltage according to the process corner based on the offsets between the process corners.
In the same field of endeavor ( e.g. automatic calibration of bandgap voltage reference generator to reduce the effect of process variations on the bandgap voltage), Zarei teaches , a first control circuit configured to control a first reference voltage to remain constant; control a second reference voltage to remain constant [ “..The automatic power control circuit shown in FIG. 1, for example, is an example of a circuit design 412 that may incorporate the bandgap voltage reference source 402.. “, col 5 lines 62-67; col 6 lines 1-19;” In operation op-amp 606 forces the voltage over the R.sub.ext (V.sub.R) to be the same as V.sub.D4, by changing the V.sub.bias. Basically, the output of op-amp 606 generates same current value for two identical current sources 620 and 622. V.sub.D4 is compared to a reference voltage (V.sub.REF), to sense the how much the diode-voltage is deviating from a constant reference voltage (V.sub.REF). The difference (V.sub.D4-V.sub.REF) is amplified by the amplifier-stage 612, and then compared to the constant reference voltages (e.g. V.sub.REF1, V.sub.REF2, V.sub.REF3, and V.sub.REF4) via several comparators 614-620. The outputs(e.g. S1, S2, S3, and S4) 502 of..”, col 7 lines 47-57; ( i.e controlling the reference voltage to remain constant)]
wherein the first control circuit is further configured to adjust the first reference voltage according to a process corner based on offsets between process corners, [ “col 1 lines 45-54; “Referring to FIGS. 4A-4C, in accordance with principles of the present disclosure a bandgap voltage reference source 402 comprises a bandgap voltage generating section 404 and a calibration section 406. The bandgap voltage reference source 402 outputs a voltage level V.sub.BG. The details of this circuit will be discussed below. In some embodiments, the bandgap voltage reference source 402 may be incorporated as a component in a larger circuit design 412. The automatic power control circuit shown in FIG. 1, for example, is an example of a circuit design 412 that may incorporate the bandgap voltage reference source 402.. some circuits such as bandgap voltage references may need to be individually calibrated in order to compensate for resulting variations in device process corners.”, col 5 lines 62-67; col 6 lines 1-19;” In operation op-amp 606 forces the voltage over the R.sub.ext (V.sub.R) to be the same as V.sub.D4, by changing the V.sub.bias. Basically, the output of op-amp 606 generates same current value for two identical current sources 620 and 622. V.sub.D4 is compared to a reference voltage (V.sub.REF), to sense the how much the diode-voltage is deviating from a constant reference voltage (V.sub.REF). The difference (V.sub.D4-V.sub.REF) is amplified by the amplifier-stage 612, and then compared to the constant reference voltages (e.g. V.sub.REF1, V.sub.REF2, V.sub.REF3, and V.sub.REF4) via several comparators 614-620. The outputs(e.g. S1, S2, S3, and S4) 502 of..”, col 7 lines 47-57; “ a bandgap voltage reference circuit, if the ratio of R2 to R1 is set for so-called "nominal" process corners, then chips whose devices have nominal process corners will behave as intended; in other words, their output voltage will vary within an acceptable range with changes in the ambient temperature. However, bandgap voltage reference circuits in chips that have fast or slow process corners, or any process corner other than a nominal process corner, may exhibit a wide swing in output voltage with changes in ambient temperature…”, col 4 lines 24-44; “ It is known that variations of a voltage V.sub.D4 (=V.sub.BE4) across the diode D4 over temperature is dependent on the actual value of V.sub.D4. ..Therefore, if the variations of V.sub.BE4 for each process corner are known, the required resistor ratio of (R.sub.2/R.sub.1), which depends on the .delta.V.sub.BE/.delta.T, can be found by generating a difference with a reference voltage (V.sub.REF). This difference is then amplified (V.sub.out) and then will be compared to several reference voltages using the comparators 614-620. ..col 8 lines 53-67; “..the comparators 614-620 would have to be able to detect voltage levels with resolution on the order of 0.03V. Such resolution imposes tight requirements for the comparators 614-620 in terms of offset voltage characteristics, and high accuracy for the reference voltages V.sub.REF1, V.sub.REF2, V.sub.REF3, and V.sub.REF4 supplied to the comparators…”, col 9 lines 1-17; Fig.7( i.e. the calibration circuit adjusts the reference voltage(V.sub.REF1, V.sub.REF2, V.sub.REF3, V.sub.REF4)according to offsets between different process corners)].
However, Zarei does not expressly disclose wherein the second control circuit is further configured to adjust the second reference voltage according to the process corner based on the offsets between the process corners.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Zarei to implement the second control circuit to adjust the second reference voltage according to the process corner based on the offsets between the process corners, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art St. Regis Paper Co.V.Bemis Co.,193 USPQ 8.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim with Zarei. Zarei’s teaching of automatic calibration of voltage regulators to reduce the effect of process variations on the bandgap voltage will substantially improve Kim’s system to provide an accurate voltage reference by compensating variations in device process corners.
However, Kim , Zarei does not expressly disclose wherein the first and second reference voltage generation circuits are configured to increase a level of the supply voltage based on determining that VSUP expected droop is higher than a predetermined value.
In the same field of endeavor(e.g. adaptive voltage modulation circuits for adjusting supply voltage to reduce supply voltage droops and minimize power consumption) Kolla teaches,
wherein the first reference voltage generation circuits are configured to increase a level of the supply voltage based on determining that VSUP expected droop is higher than a predetermined value [ [“the adaptive voltage modulation circuit 100 increases the supply voltage (V) in response to the load circuit 102 experiencing supply voltage droops for a higher percentage of the defined period (e.g., a higher throttle percentage)..”, 0023; “.. the droop detection signal 108′ is in an active state in response to detecting a supply voltage droop. .. “, 0030;” the adaptive voltage modulation circuit 300 also employs a supply voltage adjust circuit 328 that includes a counter circuit 114′ configured to count the number of cycles of the reference clock signal CLK_REF during which the supply voltage (V) is less than the droop threshold voltage (VDT′). .. ”, 0032; “, in order to adjust the supply voltage (V) based on the adjust-up and adjust-down counts UP_CNT, DN_CNT, the supply voltage adjust circuit 328 also includes an adjust-up register 338 and an adjust-down register 340. In particular, the adjust-up register 338 is configured to store an adjust-up threshold value (AU), while the adjust-down register 340 is configured to store an adjust-down threshold value (AD).. the adjust-up and adjust-down threshold values (AU), (AD) can be determined during testing of a corresponding chip and stored in the adjust-up and adjust-down registers 338, 340.”, 0034; “..the voltage adjust-up signal 118′ is initially in an inactive state, wherein the voltage adjust-up circuit 116′ generates the voltage adjust-up signal 118′ in an active state in response to the adjust-up count UP_CNT indicated by the up count signal 336(1) being greater than the adjust-up threshold value (AU) at any time during the defined period…”, 0035; “ the supply voltage controller circuit 124 is configured to increase the supply voltage (V) provided to the load circuit 102 in response to the voltage adjust-up signal 118′ being in an active state. Additionally, the supply voltage controller circuit 124 is configured to decrease the supply voltage (V) provided to the load circuit 102 in response to the voltage adjust-down signal 122′ being in an active state. “, 0037; ( i.e. increasing the supply voltage value based on the droop detection count higher than a predetermined / adjust-up threshold (i.e predetermined) value)].
However, Kolla does not expressly disclose second reference voltage generation circuits are configured to increase a level of the supply voltage based on determining that VSUP expected droop is higher than a predetermined value.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Kolla to implement second reference voltage generation circuits are configured to increase a level of the supply voltage based on determining that VSUP expected droop is higher than a predetermined value, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co.V.Bemis Co.,193 USPQ 8.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kolla with Kim in view of Zarei. Kolla’s teaching of adjusting the supply voltage based on separate adjust-up and adjust-down counts corresponding to separate adjust-up and adjust-down periods and comparing them with their respective thresholds will substantially improve Kim in view of Zarei’s system to assign a higher weight to either higher performance or greater power savings by defining the adjust-up period to be shorter in duration than then adjust-down period for higher performance or vice-versa for greater power savings[0033]
Regarding claim 19, Kim discloses, wherein the first voltage droop detection circuit and the first functional circuit are arranged adjacent to each other inside the system-on-chip[ 0131-0132; Fig.10] , the second functional circuit [ Fig.10].
However, Kim does not expressly disclose the second voltage droop detection circuit and the second functional circuit are arranged adjacent to each other inside the system-on-chip.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the second voltage droop detection circuit and the second functional circuit are arranged adjacent to each other inside the system-on-chip, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 20, Kim discloses , wherein the clock modulation circuit comprises: a first frequency divider configured to divide a frequency of the clock signal and output a first divided clock signal[0065; Fig.3B]; a second frequency divider configured to divide the frequency of the clock signal and output a second divided clock signal[0065; Fig.3B]; and a multiplexer configured to select and output any one of the first divided clock signal and the second divided clock signal as an adaptive clock signal to the first and second functional circuits, in response to the first and second detection signals [0064; 0066; 0044;0106;0179; (i.e generating a respective clock adaptive signal to the corresponding functional circuits based on the error / detection signals)].
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kolla in view Zarei as applied to claim 1 further in view of Blom et.al. (U.S Patent 9,331,707; hereinafter “Blom”; Reference cited as prior art in previous office action)
Regarding claim 11, Kolla discloses the limitations outlined in claim 1.
Zarei teaches, wherein the reference voltage generator comprises: a band gap reference circuit configured to generate a band gap reference voltage[ “Referring to FIGS. 4A-4C, in accordance with principles of the present disclosure a bandgap voltage reference source 402 comprises a bandgap voltage generating section 404 and a calibration section 406. The bandgap voltage reference source 402 outputs a voltage level V.sub.BG. The details of this circuit will be discussed below. In some embodiments, the bandgap voltage reference source 402 may be incorporated as a component in a larger circuit design 412. The automatic power control circuit shown in FIG. 1, for example, is an example of a circuit design 412 that may incorporate the bandgap voltage reference source 402...”, col 5 lines 62-67];
However, Kolla , Zarei does not expressly disclose a reference voltage buffer configured to receive the band gap reference voltage and output a digital-to-analog converter (DAC) reference voltage; a DAC configured to convert the DAC reference voltage into an analog reference voltage; and a buffer configured to output the analog reference voltage, wherein the analog reference voltage is the reference voltage.
In the same field of endeavor ( e.g. voltage generator to generate a programmable temperature compensated voltage reference), Blom teaches ,
a reference voltage buffer configured to receive the band gap reference voltage and output a digital-to-analog converter (DAC) reference voltage, a DAC configured to convert the DAC reference voltage into an analog reference voltage; [ col 2 lines 48-55; Fig.2 ; “At block 502, a precise reference voltage is generated. In an exemplary embodiment and the bandgap reference voltage generator 222 operates to generate the precise reference voltage 224.; At block 504, a digital code is converted to analog voltage based on the reference voltage. For example, the digital interface 210 outputs a digital DAC code that is input to the DAC register 214. The DAC register 214 outputs the DAC code to the multi-bit DAC 226. The multi-bit DAC 226 generates the analog voltage 228 based on the received DAC code 218 and the reference voltage 224 received from the band gap reference voltage generator 222”, col 6 lines 15-26; Fig.5] and a buffer configured to output the analog reference voltage, wherein the analog reference voltage is the reference voltage[ “At block 512, the analog voltage signal 228 output from the DAC 226 is combined with the analog compensation signal 232 output from the trim DAC 220 to generate a temperature compensated voltage signal. In an exemplary embodiment, the signal combiner 230 receives the analog voltage signal 228 and the analog compensation signal 232 output and combines these signals to generate the temperature compensated voltage signal 234. At block 514, the temperature compensated voltage signal is buffered (and/or amplified) to generate the temperature compensated programmable output voltage (VREF). For example, in an exemplary embodiment the output buffer 236 receives the temperature compensated analog signal and outputs the VREF signal.(48) ..”, col 6 lines 49-67].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kolla in view of Zarei with Blom. Blom’s teaching of generating a temperature compensated voltage reference will substantially improve Kolla in view of Zarei’s system to provide a reference voltage that reduces temperature dependent errors by implementing an on-chip digitizing temperature sensor to measure the die temperature near a bandgap voltage reference circuit.
Response to Arguments
Applicant’s arguments with respect to amended limitations for claim(s) 1, 12, 18 have been considered but are moot because the arguments do not apply to Kolla in view of Zarei ( Claims 1, 12), Kim in view of Zarei in view of Kolla ( Claim 18), references being used in the current rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Barrenscheen et.al. U.S Patent Application Publication 2009/0085551, teaches a method for monitoring the supply voltage of an electronic device includes the steps of: determining an operating condition of the electronic device, adjusting a plurality of reference voltages dependent on the operating condition of the electronic device, wherein each of the plurality of reference voltages is adjusted at a different time, and comparing the supply voltage of the electronic device with at least one of the plurality of reference voltages.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAYATHRI SAMPATH whose telephone number is (571)272-5489. The examiner can normally be reached on Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 5712701640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GAYATHRI SAMPATH/ Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/ Supervisory Patent Examiner, Art Unit 2176