Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim (s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (JP2014192497A) in view of Nitta et al. (JP 2021111710 A) hereinafter Nitta.
Regarding claim 1, Suzuki discloses a printed circuit board (7;Fig.2), comprising: an insulating layer (34;Fig.2); and a plurality of wiring layers (31,33, and 35) disposed in the insulating layer, wherein the plurality of wiring layers comprise a first wiring layer (31), a second wiring layer (33) disposed on the first wiring layer (31) , and a third wiring layer (35) disposed on the second wiring layer, the second wiring layer is thicker than each of the first and third wiring layers (see layer 33 thicker than 31 and 35), and the second wiring layer comprises one or microcircuit patterns and has an aspect ratio ( see layer 33 with a circuit pattern with an aspect ratio).
Susuki is silent with respect to the aspect ratio of the second wiring layer having a ratio of a height to a line width, being 2.4 to 3.6.
Nitta discloses the aspect ratio of a wiring layer (15 Fig.1) having a ratio of a height to a line width being 2.4 to 3.6 (see “as the lower limit of the average thickness H2 of the second wiring 15, 5 μm is preferable, 10 μm is more preferable, and 20 μm is further preferable. The upper limit of the average thickness H2 of the second wiring 15 is preferably 100 μm”; and “the minimum line width of the second wiring 15 can be appropriately set so as to satisfy the above aspect ratio, for example. For example, as the lower limit of the minimum line width of the second wiring 15μm is more preferable. The upper limit of the minimum line width of the second wiring 15 is preferably 100 μm” if the thickness is 50 micrometers and the width is 20 micrometers then the aspect ratio is 2.5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Nitta to modify the second wiring layer of Susuki in order to conduct current to perform circuit operations.
Regarding claim 2, Suzuki discloses wherein each of the first and third wiring layers comprises a ground pattern (see 31 and 35 are ground patterns), and the microcircuit pattern of the second wiring layer is a signal pattern (see 33 as a signal pattern).
Regarding claim 3, Suzuki fails to specifically discloses the claimed invention except for wherein the microcircuit pattern of the second wiring layer has a line width of substantially 1 μm, an interval between adjacent patterns, among the one or microcircuit patterns, of substantially 1 μm, and a height of substantially 3 μm. It would have been obvious to one of ordinary skill in the art at the time the invention was made to use wherein the microcircuit pattern of the second wiring layer has a line width of substantially 1 μm, an interval between adjacent patterns, among the one or microcircuit patterns, of substantially 1 μm, and a height of substantially 3 μm in order to conduct electrical current to perform circuit operations, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ233.
Claim (s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki in view of Nitta, as applied to claim 1, and further in view of Shimizu et al. (US 2024/0237203 A1) hereinafter Shimizu.
Regarding claim 12, Suzuki fails to specifically disclose comprising a plurality of build-up insulating layers, a plurality of build-up wiring layers, and a plurality of build-up via layers, the plurality of build-up insulating layers includes the insulating layer, and the plurality of build-up wiring layers includes the plurality of wiring layers.
Shimizu discloses a plurality of build-up insulating layers (21; Fig.1), a plurality of build-up wiring layers (22), and a plurality of build-up via layers (see vias 22), the plurality of build-up insulating layers includes the insulating layer, and the plurality of build-up wiring layers includes the plurality of wiring layers (see 20: Fig.1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Shimizu to modify the printed circuit board of Suzuki in order to perform circuit operations.
Regarding claim 13, Suzuki fails to specifically disclose a core layer, first and second core wiring layers respectively disposed on upper and lower surfaces of the core layer, a through-via penetrating through the core layer and connecting the first and second core wiring layers to each other.
Shimizu discloses a core layer (100; Fig.1) , first and second core wiring layers (102) respectively disposed on upper and lower surfaces of the core layer (101) , a through-via (103) penetrating through the core layer and connecting the first and second core wiring layers to each other (see 100).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Shimizu to modify the printed circuit board of Suzuki in order to perform circuit operations.
Regarding claim 14, Suzuki fails to specifically disclose the plurality of build-up insulating layers includes a plurality of first build-up insulating layers disposed on the upper surface of the core layer, and a plurality of second build-up insulating layers disposed on the lower surface of the core layer, the plurality of build-up wiring layers includes a plurality of first build-up wiring layers respectively disposed on or in the plurality of first build-up insulating layers, and a plurality of second build-up wiring layers respectively disposed on or in the plurality of second build-up insulating layers, and the plurality of build-up via layers includes a plurality of first build-up via layers respectively penetrating through at least one of the plurality of first build-up insulating layers and respectively connected to at least one of the plurality of first build-up wiring layers, and a plurality of second build-up via layers respectively penetrating through at least one of the plurality of second build-up insulating layers and respectively connected to at least one of the plurality of second build-up wiring layers.
Shimizu discloses plurality of build-up insulating layers includes a plurality of first build-up insulating layers (20) disposed on the upper surface of the core layer (100), and a plurality of second build-up insulating layers (30) disposed on the lower surface of the core layer, the plurality of build-up wiring layers includes a plurality of first build-up wiring layers (22) respectively disposed on or in the plurality of first build-up insulating layers (21), and a plurality of second build-up wiring layers (32) respectively disposed on or in the plurality of second build-up insulating layers (31), and the plurality of build-up via layers (22) includes a plurality of first build-up via layers (22) respectively penetrating through at least one of the plurality of first build-up insulating layers (20) and respectively connected to at least one of the plurality of first build-up wiring layers, and a plurality of second build-up via layers (32) respectively penetrating through at least one of the plurality of second build-up insulating layers (31) and respectively connected to at least one of the plurality of second build-up wiring layers (32).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Shimizu to modify the printed circuit board of Suzuki in order to perform circuit operations.
Allowable Subject Matter
Claims 15-18 are allowed over prior art of record.
Claims 4-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance:
Regarding claims 4-5, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein, when a thickness of the first wiring layer is defined as t1 and a thickness of the second wiring layer is defined as t2, t1 and t2 satisfy (2.1 * t1) ≤ t2 ≤ (3.9 * t1) in combination with the remaining limitations of the claim 4.
Regarding claims 6-9, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein a thickness of the second wiring layer is greater than each of an insulating distance between the first and second wiring layers and an insulating distance between the second and third wiring layers. in combination with the remaining limitations of the claim 6.
Regarding claims 10-11, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the plurality of wiring layers further comprise a fourth wiring layer disposed on the third wiring layer and a fifth wiring layer disposed on the fourth wiring layer, and the fourth wiring layer is thicker than each of the third and fifth wiring layers” in combination with the remaining limitations of the claim 6.
Regarding claims 15-18, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" a thickness of the second wiring layer is greater than each of an insulating distance between the first and second wiring layers and an insulating distance between the second and third wiring layers, and when the thickness of the second wiring layer is defined as t2, the insulating distance between the first and second wiring layers is defined as d1, and the insulating distance between the second and third wiring layers is defined as d2, t2, d1 and d2 satisfy (1.4 * d1) ≤ t2 ≤ (2.6 * d1) and (1.4 * d2) ≤ t2 ≤ (2.6 * d2) " in combination with the remaining limitations of the claim 15.
Therefore, prior art of record neither anticipates nor renders obvious the instantapplication claimed invention as a whole either taken alone or in combination.
Any comments considered necessary by applicant must be submitted no laterthan the payment of the issue fee and, to avoid processing delays, should preferablyaccompany the issue fee. Such submissions should be clearly labeled "Comments onStatement of Reasons for Allowance."
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/PETE T LEE/Primary Examiner, Art Unit 2848