Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to communications filed on 4/19/24.
Claims 1-20 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-9, 11-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11994896. Although the claims at issue are not identical, they are not patentably distinct from each other because of the claim correspondence given below:
Claim 1 of the pending application
Claim 8 of the patent 11994896
A method of maintaining correct time in different clock domains comprising: incrementing a first counter value of a first counter using a first clock signal and incrementing a second counter value of a second counter using a second clock signal, the second clock signal being slower than, and asynchronous to, the first clock signal;
A method of maintaining correct time in different clock domains comprising: incrementing a first counter value of a first counter using a first clock signal; incrementing a second counter value of a second counter using a second clock signal, the second clock signal being asynchronous to the first clock signal;
performing a first calibration of the first and second clock signals and
determining a first selected time according to a first calibration of the first and second clock signals after a first time period;
loading the first counter value as the second counter value in the second counter based at least in part on a phase relationship between the first clock signal and the second clock signal;
generating a first sampling pulse at the first selected time based on a predetermined phase relationship between the first clock signal and the second clock signal; sampling the first counter responsive to the first sampling pulse and generating a first sampled counter value; loading the first sampled counter value as the second counter value in the second counter;
and performing a second calibration based at least in part on whether an active edge of the second clock signal occurs between two active edges of the first clock signal.
and determining a second calibration when an active edge of a slower clock signal is between two active edges of a faster clock signal after passage of the first time period, the first clock signal or the second clock signal being the faster clock signal and the other of the first clock signal and the second clock signal being the slower clock signal.
For claims 2 and 12, claim 8 of the patent provides the corresponding limitations.
For claims 3 and 13, claim 13 of the patent provides the corresponding limitations.
For claims 4 and 14, claim 14 of the patent provides the corresponding limitations.
For claims 5 and 15, claim 15 of the patent provides the corresponding limitations.
For claims 6 and 16, claim 16 of the patent provides he corresponding limitations.
For claims 7 and 17, claim 10 of the patent provides the corresponding limitations.
For claims 8 and 18, claim 11 of the patent provides the corresponding limitations.
For claims 9 and 19, claim 8 of the patent provides the corresponding limitations.
For claim 11, the table for claim 1 described above provides the corresponding mappings for the limitations.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11526193. Although the claims at issue are not identical, they are not patentably distinct from each other because of the claim correspondence given below:
Claim 1 of the pending application
Claim 16 of the patent 11526193 (claim 9 plus claim 15 plus claim 16)
A method of maintaining correct time in different clock domains comprising: incrementing a first counter value of a first counter using a first clock signal and incrementing a second counter value of a second counter using a second clock signal, the second clock signal being slower than, and asynchronous to, the first clock signal;
An apparatus for maintaining correct time comprising: a first counter to increment a first counter value responsive to a first clock signal, the first clock signal having a first frequency; a second counter to increment a second counter value responsive to a second clock signal that is asynchronous to the first clock signal, the second clock signal having a second frequency; and a sample circuit to generate respective sample pulses to sample the first counter value at selected times and generate a sampled first counter value at each of the selected times, each of the selected times being based in part, on occurrence of a nominal phase alignment between the first clock signal and the second clock signal, each of the selected times being determined, at least in part, according to a passage of a first time interval associated with a lowest common multiple of a first period associated with the first frequency and a second period associated with the second frequency, multiplied by K, where K is a number greater than or equal to one, an end of the first time interval indicating the nominal phase alignment between the first clock signal and the second clock signal and the second counter value being adjusted based on the sampled first counter value.
performing a first calibration of the first and second clock signals and
The apparatus as recited in claim 9 wherein each of the selected times is further determined according to, after the first time interval, a further calibration operation to calibrate the first clock signal and the second clock signal.
loading the first counter value as the second counter value in the second counter based at least in part on a phase relationship between the first clock signal and the second clock signal;
The apparatus as recited in claim 15 wherein the further calibration operation determines when an active edge of the first clock signal occurs between two active edges of the second clock signal after the first time interval has passed.
and performing a second calibration based at least in part on whether an active edge of the second clock signal occurs between two active edges of the first clock signal.
For claims 2 and 12, claim 9 of the patent mentions generating sampling pulse to sample first counter at selected time that is based on phase relationship.
For claims 3 and 13, claim 12 mentions generating error indicating difference between two counter values (sampled second counter value is the claimed third counter value and sampled first counter value is the claimed second counter value).
For claims 4 and 14, claim 12 and claim 13 recite adjusting increment values over a number of cycles (i.e., periods) of second clock signal according to the error to adjust counter (i.e., value).
For claims 5 and 15, claim 12 of the patent provides the corresponding limitations.
For claims 6 and 16, claim 12 of the patent provides the corresponding limitations.
For claims 7 and 17, claim 13 of the patent teaches adjustment of second counter value (i.e., correction of the second counter value based on calibration criterion)
For claims 8 and 18, claim 7 of the patent provides the corresponding limitations.
For claims 9 and 19, claims 9 and 11 provide the corresponding limitations (selected time is the claimed first time period).
For claims 10 and 20, claim 9 of the patent provides the corresponding limitations.
For claim 11, the table for claim 1 described above provides the corresponding mappings for the limitations.
Claim Interpretation
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent is not met. If the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed. See Ex Parte Schulhauser. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B (MPEP 2111.04).
Claim 1 recites the limitations “loading the first counter value as the second counter value in the second counter based at least in part on a phase relationship between the first clock signal and the second clock signal; and performing a second calibration based at least in part on whether an active edge of the second clock signal occurs between two active edges of the first clock signal”. The loading of counter value is conditional as this is based on a phase relationship, i.e., loading may occur for a particular relationship only. There may be phase relationships which may not result in loading the counter value. Therefore, BRI does not include the corresponding step “loading the first counter value as the second counter value in the second counter”. Similarly, the limitation “performing a second calibration” is conditional and may not occur as it depends on “active edge of the second clock signal occurring between two active edges of the first clock signal” and BRI does not include second calibration to be performed. Claims 5-6 include mutually exclusive conditions and BRI includes none when third condition is met (values are equal) and BRI does not include the corresponding steps of claims 5-6. Claim 7, claims 9-10 recite further conditional limitations and thus, corresponding steps are not part of BRI because these steps are not required if conditions are not met. For compact prosecution, Examiner is addressing the conditional limitations and the corresponding steps as described below.
The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed. Claims 11-20 recite the system claims and the BRI includes structures corresponding to conditions.
Claim Objections
Claim 11-20 are objected to because of the following informalities:
For claim 11, line 9 recites “he”, which should be changed to –the--.
Claims 12-20 depend on claim 11 and incorporate the informalities.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7-11, 13-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haartsen et al (US Patent Application Publication 2009/0296531), in view of Franck et al (US patent 6785851).
For claim 1, Haartsen et al teach the following limitations: A method of maintaining correct time in different clock domains (Fig 1 shows two clocks CSR produced by 111 and CSLP produced by 109; these clocks provide different operations as explained in [0041]-[0044]; the method provide calibrating clocks as mentioned in [0001]) comprising: incrementing a first counter value of a first counter using a first clock signal (the first clock signal is CSR as shown in Fig 2 and Fig 3; counter 201 in Fig 2, counter 801 in Fig 8 uses CSR to increment the value; [0048] – counter 201 generates incremented counter values responsive to edges of the reference clock CSR; [0072]-[0073] 801 is a counter) and incrementing a second counter value of a second counter using a second clock signal (803 in Fig 8 is the adder that uses low power clock CSLP to add values from 801; [0073] mentions adding circuit 803 integrates values generated by counter 801 at rising edges of clock signal CSLP; an adder circuit includes a counter; Fig 13 shows the IP(I) column that illustrates example values of adder 803, which sufficiently teaches a counter incrementing a second counter value using clock CSLP), the second clock signal being slower than, and asynchronous to, the first clock signal (Fig 7 shows two clocks where CSLP is slower than CSR; [0041]-[0042] Fig 1 - two clocks are from different sources with CSR having higher frequency and CSLP having lower frequency, phase difference/offset [0075]-[0076] – that is, clocks are asynchronous to each other); performing a first calibration of the first and second clock signals (Fig 15 and [0080] mention about multiple calibration; first wake period has first calibration and second wake period has second calibration) and loading the first counter value as the second counter value in the second counter (the first counter value 812 in 801 (shown as P(I)) is loaded into counter 803 (shown as IP(I)) in Fig 13 at T = 0.031 and I = 1, that is, at the rising edge of CSLP clock; [0072]-[0073] – current value of IP is added to current value of P and the result is saved into IP – the current value is 0 and therefore, at the rising edge of the CSLP, IP(I) loads the value of P(I) at I =1 as shown in Fig 13) based at least in part on a phase relationship between the first clock signal and the second clock signal (counter 801 is clocked by CSR and counts the edges of the CSR and 803 loads the value at the rising edge of CSLP; in other words, value in 803 is loaded at the rising edge of CSLP and values are the count of rising edges of CSR for each rising edge of CSLP; thus the loading is based on phase relationship between two clock signals); and performing a second calibration (Fig 14 and Fig 15; [0033] – calibration operations) based at least in part on whether an active edge of the second clock signal occurs between two active edges of the first clock signal (Fig 3, [0050]-[0052] [0070] explains how the counter values P(0) – P(N) are collected, which includes taking counter output P(i) at the edges of CSLP, therefore active edge of CSLP is detected by the calibration circuit so as to realize the correct location on CSR to find the correct value of counter 201/801 to be sampled; Fig 3 shows active edge S(1) falls between two active edges and therefore, the count value P(1) = 1 (or other value depending on the phase relationships) will be sampled; if CSR has lagging phase relationship with CSLP, then S(1) would not be within two active edges and P(1) = 0 would be sampled; S(2) that samples P(2) and the line from S(2) shows that it falls between two edges and the count value corresponding to the edge before the sampling point is sampled accordingly; thus the sampling of the values are based on whether active edge of the second clock signal CSLP occurs within two active edges of the first clock CSR).
About the limitation, incrementing a second counter value of a second counter using a second clock signal, Haartsen mentions 803 to use second clock CSLP to increment its value as shown in Fig 13 (as IP(I)) and [0073]. Haartsen mentions 803 as adder/integrator ([0073]), not as a counter. As explained above, the adder is a type of counter. For further clarification, Examiner cites Franck et al that mentions adder, register combinations can be collectively referred to as a counter (lines 45-55 of col 3 and lines 37-41 of col 4). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to implement an adder as a counter, since counter circuitries are available and easy to construct an adder.
For claim 7, Haartsen teaches choosing new frequency to minimize error ([0077]), which will correct the second counter. This can be performed after the calibration since calibration is recurring ([0058][0064] [0077]).
For claim 8, Haartsen Fig 13 – i represents the number of cycles of low frequency clock CSLP and P(I) represents the number of clock cycles high frequency first clock CSR. With the moving average calculation explained in [0078]-[0082], the accurate fCSLP can be determined and then a suitable frequency can be chosen to further minimize the error ([0077]). The new frequency of CSLP can increase the three counters by an increment. Since the previous calibration is based on moving average and the new frequency value is based on previous calibration, such increase of count value for new frequency can be termed as average increment. Thus, the counts have increased counter values by first and second average increments for the two number of clock cycles of the two clock signals.
For claim 9, Haartsen teaches loading to IP(I) after passage of time 0.031 ms.
For claim 10, as mentioned above, BRI does not include loading of the first counter value as the second counter value and the corresponding time period..
For claim 11, Haartsen et al teach the following limitations: An apparatus comprising: a first counter to increment a first counter value responsive to a first clock signal , the first clock signal having a first frequency (the first clock signal is CSR as shown in Fig 2 and Fig 3; counter 201 in Fig 2, counter 801 in Fig 8 uses CSR to increment the value; [0048] – counter 201 generates incremented counter values responsive to edges of the reference clock CSR; [0072]-[0073] 801 is a counter) and a second counter to increment a second counter value responsive to a second clock signal (803 in Fig 8 is the adder that uses low power clock CSLP to add values from 801; [0073] mentions adding circuit 803 integrates values generated by counter 801 at rising edges of clock signal CSLP; an adder circuit includes a counter; Fig 13 shows the IP(I) column that illustrates example values of adder 803, which sufficiently teaches a counter incrementing a second counter value using clock CSLP) that is slower than, and asynchronous to, the first clock signal (Fig 7 shows two clocks where CSLP is slower than CSR; [0041]-[0042] Fig 1 - two clocks are from different sources with CSR having higher frequency and CSLP having lower frequency, phase difference/offset [0075]-[0076] – that is, clocks are asynchronous to each other); and a sample circuit (calibration circuit shown in Fig 1, Fig 2 and Fig 8) that performs a first calibration of the first and second clock signals (Fig 15 and [0080] mention about multiple calibration; first wake period has first calibration and second wake period has second calibration), loads the first counter value as the second counter value in the second counter (the first counter value 812 in 801 (shown as P(I)) is loaded into counter 803 (shown as IP(I)) in Fig 13 at T = 0.031 and I = 1, that is, at the rising edge of CSLP clock; [0072]-[0073] – current value of IP is added to current value of P and the result is saved into IP – the current value is 0 and therefore, at the rising edge of the CSLP, IP(I) loads the value of P(I) at I =1 as shown in Fig 13) based at least in part on a phase relationship between he first clock signal and the second clock signal (counter 801 is clocked by CSR and counts the edges of the CSR and 803 loads the value at the rising edge of CSLP; in other words, value in 803 is loaded at the rising edge of CSLP and values are the count of rising edges of CSR for each rising edge of CSLP; thus the loading is based on phase relationship between two clock signals), the sample circuit further performs a second calibration (Fig 14 and Fig 15; [0033] – calibration operations) based at least in part on whether an active edge of the second clock signal occurs between two active edges of the first clock signal (Fig 3, [0050]-[0052] [0070] explains how the counter values P(0) – P(N) are collected, which includes taking counter output P(i) at the edges of CSLP, therefore active edge of CSLP is detected by the calibration circuit so as to realize the correct location on CSR to find the correct value of counter 201/801 to be sampled; Fig 3 shows active edge S(1) falls between two active edges and therefore, the count value P(1) = 1 (or other value depending on the phase relationships) will be sampled; if CSR has lagging phase relationship with CSLP, then S(1) would not be within two active edges and P(1) = 0 would be sampled; S(2) that samples P(2) and the line from S(2) shows that it falls between two edges and the count value corresponding to the edge before the sampling point is sampled accordingly; thus the sampling of the values are based on whether active edge of the second clock signal CSLP occurs within two active edges of the first clock CSR).
About the limitation, incrementing a second counter value of a second counter using a second clock signal, Haartsen mentions 803 to use second clock CSLP to increment it’s value as shown in Fig 13 (as IP(I)) and [0073]. Haartsen mentions 803 as adder/integrator ([0073]), not as a counter. As explained above, the adder is a type of counter. For further clarification, Examiner cites Franck et al that mentions adder, register combinations can be collectively referred to as a counter (lines 45-55 of col 3 and lines 37-41 of col 4). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to implement an adder as a counter, since counter circuitries are available and easy to construct an adder.
For claim 13, Haartsen teaches error generation (Fig 10 – Fig 12), but does not mention that the error indicating a difference between two values of a second counter. However, Fig 9 mentions that estimated frequency is a function of IP and IIP counter. Therefore, for each setting of the two frequencies, calibration window and delta phi, the frequency value of IP counter corresponds to one value of estimated fCSLP and error. As [0077] mentions, another setting with another delta phi (keeping other values same) can be used to get less error value. As the fCSLP can be expressed as IP counter, the second setting for second estimate of fCSLP will provide another IP counter value. That is, two error values will correspond to two counter values. Thus, the error difference (which is also an error) can be expressed as the difference of counter values. It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to express error as the difference of counter values, since it provides as easier way to visualize the error in the calibration.
For claim 14, Haartsen Fig 5, [0058]-[0064] mentions about taking a moving average of multiple wake periods to get a best fit (i.e., minimization of error) so as to accurately calculate the low frequency clock signal (multiple alpha is combined to get average alpha). Thus, the increment values are adjusted over multiple cycles of second clock CSLP ([0064] moving average includes counter values from different wake periods may be combined using weighted, non-weighted averaging and exponential forgetting). [0077] further mentions choosing frequency to reduce error. Therefore, with the moving average of alpha/counter values, the error can be calculated accurately to adjust phase offset/increment to minimize error ([0075] and [0077]), which will be reflected in the correct counter values.
For claims 15 and 16, moving average (weighted/non-weighted) and exponential forgetting ([0064][0059] Haartsen) includes increasing/decreasing values for cycles of second clock ([i.e., multiple wake periods [0059][0053][0064]). As mentioned above, Haartsen’s equation in Fig 9 can reflect the counter value as an indication of fCSLP and the error when other factors, such as N, fCSR, calibration window are constant. When phase offset/increment changes ([0077]), the counter IP values and error values differ. Therefore, after changing to a new phase offset/increment (which changes counter values positively or negatively), the new calibration for new wake periods will consider new moving averages of counter values and alpha.
For claim 17, Haartsen teaches choosing new frequency to minimize error ([0077]), which will correct the second counter. This can be performed after the calibration since calibration is recurring ([0058][0064] [0077]).
For claim 18, Haartsen Fig 13 – i represents the number of cycles of low frequency clock CSLP and P(I) represents the number of clock cycles high frequency first clock CSR. With the moving average calculation explained in [0078]-[0082], the accurate fCSLP can be determined and then a suitable frequency can be chosen to further minimize the error ([0077]). The new frequency of CSLP can increase the three counters by an increment. Since the previous calibration is based on moving average and the new frequency value is based on previous calibration, such increase of count value for new frequency can be termed as average increment. Thus the counts have increased counter values by first and second average increments for the two number of clock cycles of the two clock signals.
For claim 19, Haartsen teaches loading to IP(I) after passage of time 0.031 ms.
Claim(s) 2-6, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haartsen et al (US Patent Application Publication 2009/0296531), in view of Franck et al (US patent 6785851), further in view of Kwon et al (US Patent Application Publication 2019/0332322).
For claims 2 and 12, sample collections are described in [0061] and [0064]. In Fig 2 and [0050] Haartsen, the write command provides the signal to sample from counter 201 to memory 203 (Haartsen). Haartsen in view of Franck does not explicitly mention about pulse. The write operation includes pulse to write into the memory ([0064] Kwon). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to use a pulse to write into the memory, since that would facilitate the correct operation of writing.
For claim 3, Haartsen teaches error generation (Fig 10 – Fig 12), but Haartsen, Franck or Kwon does not mention that the error indicating a difference between two values of a second counter. However, Fig 9 Haartsen mentions that estimated frequency is a function of IP and IIP counter. Therefore, for each setting of the two frequencies, calibration window and delta phi, the frequency value of IP counter corresponds to one value of estimated fCSLP and error. As [0077] mentions, another setting with another delta phi (keeping other values same) can be used to get less error value. As the fCSLP can be expressed as IP counter, the second setting for second estimate of fCSLP will provide another IP counter value. That is, two error values will correspond to two counter values. Thus, the error difference (which is also an error) can be expressed as the difference of counter values. It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to express error as the difference of counter values, since it provides as easier way to visualize the error in the calibration.
For claim 4, Haartsen Fig 5, [0058]-[0064] mentions about taking a moving average of multiple wake periods to get a best fit (i.e., minimization of error) so as to accurately calculate the low frequency clock signal (multiple alpha is combined to get average alpha). Thus, the increment values are adjusted over multiple cycles of second clock CSLP ([0064] moving average includes counter values from different wake periods may be combined using weighted, non-weighted averaging and exponential forgetting). [0077] further mentions choosing frequency to reduce error. Therefore, with the moving average of alpha/counter values, the error can be calculated accurately to adjust phase offset/increment to minimize error ([0075] and [0077]), which will be reflected in the correct counter values.
For claims 5 and 6, moving average (weighted/non-weighted) and exponential forgetting ([0064][0059] Haartsen) includes increasing/decreasing values for cycles of second clock ([i.e., multiple wake periods [0059][0053][0064]). As mentioned above, Haartsen’s equation in Fig 9 can reflect the counter value as an indication of fCSLP and the error when other factors, such as N, fCSR, calibration window are constant. When phase offset/increment changes ([0077]), the counter IP values and error values differ. Therefore, after changing to a new phase offset/increment (which changes counter values positively or negatively), the new calibration for new wake periods will consider new moving averages of counter values and alpha.
Allowable Subject Matter
Claim 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and to overcome the double patenting rejection by submitting the terminal disclaimer.
Conclusion
PTO-892 cites few additional references that provide teachings of the clock calibration, but are not relied upon for rejections.
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/FAHMIDA RAHMAN/Primary Examiner, Art Unit 2175