DETAILED ACTION
Status of Claims
Claims 1, 10-11 are amended.
Claims 1-20 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/22/2026 has been entered.
Priority
Applicant’s claim for the benefit of a prior-filed application filed in PCT IN 202041045051 on 10/16/2020 under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites “wherein the first/second constant inter-chirp time is determined as a sum of the nominal inter-chirp time and the second chirp dither value”. It is unclear what the difference is between constant inter-chirp time and nominal inter-chirp time. The term “nominal inter-chirp time” is not provided in the instant specification and any inter-chirp dithering would be included in the inter-chirp time, not additive. The examiner has interpreted this limitation as “wherein the interval between successive chirps in a series of chirps is determined as an inter-chirp time” (see instant specification [0036-0037]).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Narayana (US 20200284874).
Regarding Claim 1, Narayana discloses the following limitations:
A non-transitory computer-readable storage device storing machine instructions that, when executed by one or more processors, cause the one or more processors to: (Narayana – [0033])
determine a first constant inter-chirp time with respect to a first series of chirps constituting a first radar frame of chirps, (Narayana – [0002] The local oscillator is configured to receive the one or more chirp control signals, and generate a frame comprising first, second, and third chirps, each chirp having a chirp start frequency, wherein the frame further has an idle time between the chirps. [0036] In at least one example, the programmable timing engine 242 includes functionality to receive chirp parameter values from the control module 226 for a sequence of chirps in a radar frame and to generate chirp control signals that control the transmission and reception of the chirps in a frame based on the parameter values. In some examples, the chirp parameters are defined by the radar system architecture and may include, for example, a transmitter enable parameter for indicating which transmit channels to enable, a chirp frequency start value, a chirp frequency slope, an ADC sampling time, a ramp end time, a transmitter start time, etc. In examples of the present disclosure, the control module 226 and programmable timing engine 242 are configured to dither the chirp start frequency, the ADC sampling window start time (e.g., when to begin sampling data received from the ADC 218A), and/or the idle time between chirps.)
in which the first constant inter-chirp time indicates a delay between a start of transmission of sequential chirps of the first series of chirps and is constant for all chirps within the first series of chirps, the first constant inter-chirp time based on a first chirp dither value; and (Narayana – [0002], [0036], [0058] For example, the control module 226 causes the programmable timing engine 242 to vary the idle time between chirps such that a first idle time between first and second chirps is different than a second idle time between second and third chirps, such that the effective inter-chirp time is approximately the same from chirp to chirp, when taking into account the dithered chirp start frequency and ADC sampling window start time.)
determine a second constant inter-chirp time with respect to a second series of chirps constituting a second radar frame of chirps, in which the second constant inter-chirp time is different than the first constant inter-chirp time and indicates a delay between a start of transmission of sequential chirps of the second series of chirps and is constant for all chirps within the second series of chirps, (Narayana – [0036], [0058])
the second inter-chirp time based on a second chirp dither value that is different than the first chirp dither value. (Narayana – [0036], [0058])
Regarding Claim 2, Narayana further discloses:
wherein the machine instructions, when executed by the one or more processors, further cause the one or more processors to: determine a first slope for each chirp of the first series of chirps; and (Narayana – [0036])
determine a second slope for each chirp of the second series of chirps, in which the second slope is different than the first slope and is based on the first slope and a slope dither value. (Narayana – [0036], [0058])
Regarding Claim 3, Narayana further discloses:
wherein the machine instructions, when executed by one or more processors, further cause the one or more processors to: (Narayana – [0033])
determine a chirp dither range; and determine the first and second chirp dither values such that they are within the chirp dither range. (Narayana – [0036], [0027] In at least one example, the processing unit 110 determines a distance and velocity of a detected object, for example, according to aspects of the present disclosure in which parameters of the FMCW radar system 100 are dithered. Examples of this disclosure may include dithering a chirp start frequency from one chirp to the next, dithering an ADC sampling window start time from one chirp to the next, and dithering an idle time between chirps. As a result of dithering various parameters of the FMCW radar system 100, IF signal leakage to other velocities is avoided for both stationary and moving objects, which mitigates the influence of spurious signals on object distance/velocity determinations.)
Regarding Claim 4, Narayana further discloses:
wherein the machine instructions, when executed by the one or more processors, further cause the one or more processors to: (Narayana – [0033])
determine a chirp slope range; and (Narayana – [0027], [0036])
determine the slope dither value such that it is within the chirp slope dither range. (Narayana – [0027], [0036])
Regarding Claim 5, Narayana further discloses:
wherein the machine instructions, when executed by the one or more processors, further cause the one or more processors to: (Narayana – [0033])
determine a third inter-chirp time with respect to a third series of chirps, the third inter-chirp time based on the chirp period and a third chirp dither value that is different from the first chirp dither value and different from the second chirp dither value. (Narayana – [0036])
Regarding Claim 6, Narayana further discloses:
the machine instructions, when executed by the one or more processors, further cause the one or more processors to: (Narayana – [0033])
generate chirp configuration signals to cause a radar circuit to: generate the first series of chirps with the first inter-chirp time; and generate the second series of chirps with the second inter-chirp time. (Narayana – [0036])
Regarding Claim 7, Narayana further discloses:
wherein the machine instructions, when executed by the one or more processors, further cause the one or more processors to generate chirp configuration signals to cause a radar circuit to: (Narayana – [0033])
generate the first series of chirps with the first inter-chirp time and the first slope; (Narayana – [0036])
generate the second series of chirps with the second inter-chirp time and the second slope. (Narayana – [0036])
Regarding Claim 8, Narayana further discloses:
wherein: each chirp of the first series of chirps has a first bandwidth, and the first slope is determined based on the first bandwidth; and (Narayana – [0036])
each chirp of the second series of chirps has a second bandwidth, and the second slope is determined based on the second bandwidth. (Narayana – [0036])
Regarding Claim 9, Narayana further discloses:
wherein the first series of chirps represents a first frame of chirps, the second series of chirps represents a second frame of chirps, and the third series of chirps represents a third frame of chirps, (Narayana – [0036], [0002] generate a frame comprising first, second, and third chirps, each chirp having a chirp start frequency, wherein the frame further has an idle time between the chirps. [0019] After each sequence of chirps, there may be some idle time (e.g., inter-frame idle time) to allow for processing the radar signals resulting from the reflected chirps. The acquisition time of a sequence of chirps, and the subsequent inter-frame idle time, together may form a radar frame.)
wherein the machine instructions, when executed by the one or more processors, further cause the one or more processors to: (Narayana – [0033])
determine a first frame period representing a length of time from a start of the first frame of chirps to a start of the second frame of chirps; and (Narayana – [0002], [0019], [0036])
determine a second frame period representing a length of time from a start of the second frame of chirps to a start of the third frame of chirps, in which the second frame period is different than the first frame period and is based on the first frame period and a frame dither value. (Narayana – [0002], [0019], [0036])
Regarding Claim 10, Narayana further discloses:
wherein the machine instructions, when executed by the one or more processors, further cause the one or more processors to: (Narayana – [0033])
determine a nominal inter-chirp time, wherein the first constant inter-chirp time is determined as a sum of the nominal inter-chirp time and the first chirp dither value; and (Narayana – [Fig. 10A-B], [0002], [0036], [0054-0055])
the second constant inter-chirp time is determined as a sum of the nominal inter-chirp time and the second chirp dither value, the second chirp dither value being different than the first chirp dither value. (Narayana – [Fig. 10A-B], [0002], [0036], [0054-0055])
Regarding Claim 11, Narayana discloses the following limitations:
A radar circuit comprising: (Narayana – [0001] In accordance with at least one example of the disclosure, a method for a radar system includes transmitting, by a transmit channel of the radar system, a frame comprising first, second, and third chirps.)
an oscillator configured to receive chirp configuration signals and generate n series of chirps based on the chirp configuration signals, (Narayana – [0002])
including generate each series of chirps of the n series of chirps with a respective constant inter-chirp time that is constant for all chirps within each respective series of chirps, wherein the constant inter-chirp time is different for each series of chirps of the n series of chirps and each series of chirps of the n series of chirps constitutes a frame; and (Narayana – [0002], [0036])
transmitter circuitry coupled to the oscillator, the transmitter circuitry configured to transmit each series of chirps with the respective constant inter-chirp time. (Narayana – [0002], [0036])
Regarding Claim 12, Narayana further discloses:
wherein the chirp configuration signals specify chirp slope information, and, (Narayana – [0036])
for each series of chirps of the n series of chirps, the oscillator is further configured to generate each chirp with a respective slope based on the chirp slope information, in which the respective slope for each series of chirps is different. (Narayana – [0036])
Regarding Claim 13, Narayana further discloses:
in which the oscillator is configured to be coupled to processing circuitry that is configured to generate the chirp configuration signals. (Narayana – [0002], [0036])
Regarding Claim 14, Narayana further discloses:
wherein the processing circuitry includes a controller and a signal processor coupled to the controller. (Narayana – [0002], [0033])
Regarding Claim 15, Narayana further discloses:
wherein: the processing circuitry is configured to determine a nominal chirp period Tc and n distinct chirp dither values, (Narayana – [0002], [0033], [0036])
including a respective chirp dither value for each series of chirps that is different for each series of chirps; and the respective inter-chirp time of each series of chirps is determined as a sum of Tc and the respective chirp dither value. (Narayana – [Fig. 10A-B], [0002], [0019], [0036], [0054-0055])
Regarding Claim 16, Narayana further discloses:
wherein the processing circuitry is further configured to determine a chirp dither range, each of the respective chirp dither values being with the chirp dither range. (Narayana – [0027], [0036])
Regarding Claim 17, Narayana further discloses:
wherein the processing circuitry is further configured to: determine the nominal chirp period Tc based on a threshold unambiguous velocity associated with the radar circuit; and (Narayana – [Fig. 10A-B], [0002], [0036], [0054-0055])
determine a maximum chirp dither defining an upper end of the chirp dither range based on a threshold deviation from the threshold unambiguous velocity. (Narayana – [Fig. 10A-B], [0002], [0027], [0036], [0054-0055])
Regarding Claim 18, Narayana further discloses:
wherein each series of chirps of the n series of chirps is a frame of chirps, wherein the processing circuitry is further configured to: (Narayana – [0002], [0019], [0036])
determine a nominal frame period TF; (Narayana – [0002], [0019], [0036])
determine a frame dither range; (Narayana – [0002], [0019], [0027], [0036])
determine, for each frame of chirps, a respective frame dither value within the frame dither range; and (Narayana – [Fig. 10A-B], [0002], [0019], [0027], [0036], [0054-0055])
determine a respective frame period for each frame of chirps as a sum of TF and the respective frame dither value. (Narayana – [Fig. 10A-B], [0002], [0019], [0027], [0036], [0054-0055])
Regarding Claim 19, Narayana further discloses:
wherein the transmitter circuitry is further configured to transmit each frame of chirps with the respective inter-chirp time and with the respective frame period. (Narayana – [0002])
Regarding Claim 20, Narayana further discloses:
further comprising: receiver circuitry coupled to the transmitter circuitry and to the oscillator. (Narayana – [0002])
Response to Arguments
Applicant’s arguments, see Page 7, filed 05/22/2026, with respect to the rejection under 35 U.S.C. § 112(b) have been fully considered and are not persuasive. The amended claim 10 raises a new issues for rejection under 35 U.S.C. § 112(b) (see 35 U.S.C. § 112(b) section).
Applicant’s arguments, see Pages 7-8, filed 05/22/2026, with respect to the rejection under 35 U.S.C. § 102(a)(1) have been fully considered and are not persuasive. Applicant argues that Narayama does not disclose “Claim 1 requires a first constant inter-chirp time for a first series of chirps (constant throughout that series) based on a first chirp dither value; and a second constant inter-chirp time for a second series of chirps (constant throughout that series) based on a second chirp dither value that is different than the first chirp dither value. Claim 11 requires an oscillator configured to generate n series of chirps, each series with a respective constant inter-chirp time, wherein the constant inter-chirp time is different for each series.” as amended. The examiner disagrees, Narayana [0002] is now cited to further disclose the amended claims stating “generate a frame comprising first, second, and third chirps, each chirp having a chirp start frequency, wherein the frame further has an idle time between the chirps” to provide an embodiment where only the idle time between frames is concerned. When considering Narayana [0002] and [0036] as a whole, it is clear that programmable timing engine 242 is disclosed to provide the frame, chirp, dither, and inter-chirp configurations as claimed.
Applicant's remaining arguments amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims is understandable and distinguishable from other inventions.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON JAMES HENSON whose telephone number is (703)756-1841. The examiner can normally be reached Monday-Friday 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Resha H. Desai can be reached at (571) 270-7792. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRANDON JAMES HENSON/Examiner, Art Unit 3648
/BERNARR E GREGORY/Primary Examiner, Art Unit 3648
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