DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This final office action is responsive to Applicants' response filed on 04/23/26. Claims 1-4 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-12, 14-15 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 20220407423 A1)
Regarding claim 1. Chen teaches a frequency inverter [fig 5A-7, circuit between Motor and Bat] comprising: at least three diodes [diodes in fig 5A] comprising a first diode [see S5]; at least two inductors [L1/L2] comprising a first inductor and a second inductor, wherein the first diode discharges the first inductor and the second inductor [diode helps discharge inductors since bidirectional topology S5 diode allows current to travel to UH]; at least one depolarized capacitor [“depolarized capacitor C2” has been interpreted as having a connection in series with inductor allowing for the energy in the inductor to induce a voltage on the capacitor when the inductor is being discharge by altering its polarity, thus, it de-polarizes the inductors terminals, C2] connected to inverter output terminals; a first, a second [S1/S2], a third, and a fourth switch [S3/S5], wherein at least two of the four switches are current bidirectional keys, wherein the first and the second switches are closed when the third and the fourth switches are open [fig 6A], and wherein the third and fourth switches are closed when the first and the second switches are open [Fig 6D]; and a control circuit [i.e. controller for circuit] configured to control the switches.
Regarding claim 2. Chen teaches the frequency inverter, of claim 1, wherein the control circuit is a hysteresis comparator [¶45].
Regarding claim 3. Chen teaches the frequency inverter, of claim 1, wherein a capacitor is connected in parallel to a load [Cf’, fig 21].
Regarding claim 6. Chen teaches the frequency inverter of claim 1, wherein the first switch is coupled to the first diode and a first terminal of the first inductor [coupled is interpreted as connected between intervening elements, all circuit components are coupled for being in same die].
Regarding claim 7. Chen teaches the frequency inverter of claim 6, wherein a second terminal of the first inductor is coupled to a second diode of the at least three diodes and to the second switch [coupled is interpreted as connected between intervening elements, all circuit components are coupled for being in same die].
Regarding claim 8. Chen teaches the frequency inverter of claim 7, wherein the third switch is coupled to a third diode of the at least three diodes and to a first terminal of the second inductor [coupled is interpreted as connected between intervening elements, all circuit components are coupled for being in same die].
Regarding claim 9. Chen teaches the frequency inverter of claim 8, wherein a second terminal of the second inductor is coupled to the first diode and to the fourth switch [coupled is interpreted as connected between intervening elements, all circuit components are coupled for being in same die].
Regarding claim 10. Chen teaches the frequency inverter of claim 6, further comprising a power source coupled to a second diode of the at least three diodes [coupled is interpreted as connected between intervening elements, all circuit components are coupled for being in same die].
Regarding claim 11. Chen teaches the frequency inverter of claim 1, wherein the frequency inverter does not include an output filter [analogues to applicants’ invention].
Regarding claim 12. Chen teaches the frequency inverter of claim 1, further comprising a first resistor in series with a second resistor, wherein the first and second resistors are in parallel to the depolarized capacitor [parallel is interpreted as coupled next to].
Regarding claim 14. Chen teaches the frequency inverter of claim 1, wherein the first switch and the fourth switch are bidirectional [switches are bidirectional as per ¶19].
Regarding claim 15. Chen teaches the frequency inverter of claim 14, wherein the second switch and the third switch are unidirectional [only one current flows in cited switches].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20200127581 A1) in view of Hayashi (US 20220311356 A1)
Regarding claim 4. Chen teaches the frequency inverter, of claim 1.
However, Chen does not explicitly mention wherein a voltage divider is connected in parallel to a load, and wherein a voltage sample is sent from a middle of the voltage divider to the control circuit.
Hayashi teaches wherein a voltage divider is connected in parallel to a load, and wherein a voltage sample is sent from a middle of the voltage divider to the control circuit [fig 5, 10-11 with fig 7, 17].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Hayashi in order to provide step down version of the output voltage makes it more manageable so that the controller can handle it without needing extra hardware.
Claims 5, 13 rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20200127581 A1) in view of Hussein et al. (US 20030002298 A1)
Regarding claim 5. Chen teaches the frequency inverter of claim 2,
However, Chen does not explicitly mention a circuit wherein the input of the hysteresis comparator is a non-inverting input.
Hussein teaches a circuit wherein the input of the hysteresis comparator is a non-inverting input [¶109].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Hussein in order to provide a circuit that prevents rapid, noisy or unintended switching by introducing unwanted thresholds.
Regarding claim 13. Chen teaches the frequency inverter of claim 2.
However, Chen does not explicitly mention a circuit further comprising a third resistor coupled to an input of the hysteresis comparator and a fourth resistor coupled to an output coupled of the hysteresis comparator.
Hussein teaches a circuit further comprising a third resistor coupled to an input of the hysteresis comparator and a fourth resistor coupled to an output coupled of the hysteresis comparator [¶109].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Hussein in order to provide a circuit that prevents rapid, noisy or unintended switching by introducing unwanted thresholds.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Crystal Hammond, can be reached on (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/ Examiner, Art Unit 2838
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