Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the communication filed on 04/19/2024.
Claims 1-20 are pending and addressed in the Action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-9, 11, 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over
Ford et al., US Pat. No. 8,185,724 B2, in view of Atamaner et al., “Detecting Errors in Instructions with Bloom Filters”, 2017, IEEE, 4 pages.
As per Claim 1: Ford discloses the limitations in bold below:
1. A data processing apparatus comprising:
storage circuitry configured to store a data value derived from a plurality of memory addresses associated with a stream of instructions;
(See col. 1, lines 61-67: “The signals being monitored may take a variety of forms, and in one embodiment may identify data addresses and/or data values passing within the integrated circuit. In such instances, the watchpoint logic may for example be coupled to a bus over which a load store unit of a processor communicates with memory. As another example, the signals being monitored may identify instruction addresses,”, col. 7, lines 54-59, “An example of such a situation may be where the monitoring logic reviews instruction addresses issued by a prefetch unit to memory.
These prefetched instructions are then typically stored in a buffer, from where they may later be routed to an execution unit of the processing logic for execution.”, and Fig. 1, Instruction Cache and Data Cache)
[membership query circuitry configured to perform an approximate set membership query] against the data value of a memory address associated with a current one of the instructions and in response to [the approximate set membership query] being positive, to issue the memory address to confirmation circuitry;
(See Fig. 2, with Query value in bits enters in to the circuit 100, FIG. 2 incorporates
a Bloom filter saturating counter vector 120, and Fig. 7: referred to Bloom Filters: “circuitry”, and
Col. 1, lines 46-55: “In accordance with a known technique for monitoring values of particular signals, one or more watchpoint registers are provided for specifying individual values or ranges of values of interest. Such watchpoint mechanisms then compare values of particular signals occurring at a predetermined place within the integrated circuit (*) (for example occurring over a particular bus path) with the values or ranges specified in the one or more watchpoint registers (**), and in the event of a match, generate a trigger signal.”.
See col. 4, lines 3-11 “Using the PC value, the identified Bloom filter vector is accessed directly using predetermined bits of the PC value, and if any accessed bit in the Bloom filter vector is zero, it is determined that the PC value does not belong to the acceptable set of PC values for that memory address. Otherwise the element may belong to the set. If it is determined that a bit accessed in the Bloom filter vector is zero, and hence the PC value definitely does not belong to the set, then a trigger is issued to trigger the monitoring function”. And further see in col.14, lines 5-11.
Within the cites above, the Superscript (**) indicated with the values or ranges specified in watchpoint registers reads on “…the data value of a memory address” and the superscript (*) indicated with occurring values or particular signals reads on “a current one of the instructions”. Those in (*) and (**) are compared, and if matched it issues a ‘trigger signal’. It reads “being positive” and “to issue the memory address to confirmation circuitry”. The Bloom filter addressed in col. 4 is for to configure the PC value in the range, and if the vector value of the Bloom is zero, the PC value of memory address is not in the range; in another word, if the positive value, it is in the range, is a confirmation.)
In Fig. 4, the Bloom Filter that acts configuration for (*) and (**) is a circuit, and Box 310 that acts the check is false hits TRUE, reads the limitation of ‘confirmation circuitry’.
Ford does not explicitly address the limitations of “membership query circuitry configured to perform an approximate set membership query” .
Ford further discloses,
and halt circuitry configured to halt execution of the stream of instructions by processing circuitry in response to at least one condition being met, the at least one condition comprising a positive indication from the confirmation circuitry that the memory address is one of the plurality of memory addresses.
(See Fig. 4, the halt circuitry is referred to a logic that triggers Debug mode . The circuit that represents box 330 is to perform:
See col. 1, lines 27-31, “Often in such debug applications, it is desirable to detect when certain predetermined values of signals occur and on such occurrence of a predetermined value to halt execution of the program and pass over control to a debug tool.”, and lines 54-56, “When used in debug applications, this trigger signal may be used, for example, to halt execution of the program and pass over control to the debug application.”. And incorporated with Fig. 4, referred to col. 4, lines 8-11 that addresses the filter carries query data.)
Ford addresses the circuit of Bloom Filter to perform query values (as in Fig. 2), but
Ford does not explicitly address “membership query circuitry configured to perform an approximate set membership query”.
Per above limitations for performing an approximate set membership query,
Atamaner discloses the limitation of, “membership query circuitry configured to perform an approximate set membership query” (Atamaner: see p, 2, Sec. III, left col., “Bloom filters are widely used probabilistic data structures that store the membership information of a set of elements and on which a query can be run to check whether an element belongs to the set or not”, and Figure 4, in p. 3 with ‘Bloom Filter’ to receive query data , i.e. based on the description of “Bloom Filter”, the data enters the filter is “an approximate set membership query” because this query is fetch instruction corresponded with fetch instruction in decode. The Bloom filter detects a condition and issues ‘if positive’ for execution or ‘if negative’ to halt.
Therefore, it would be obvious to an ordinary of skills in the art before the effective filing of the application to combine the teaching of the Bloom filter circuit of Atamaner, a circuit for storing membership query and for detecting setting condition, with the teaching of Ford using the Bloom filter for issuing halting execution when a positive condition match. The combination would yield predictable results because membership query circuitry is known as a Bloom filter circuit, and it would be used as a standard circuit in detecting conditions set in memory instructions.
As per Claim 2: Ford and combining Atamaner, where
Ford further discloses,
2. The data processing apparatus according to claim 1, wherein
the memory addresses comprise program counter values of those of the instructions at which a breakpoint is set.
(Ford: Col. 1, line 61 to Col. 2, line 7, referred to “…in one embodiment may identify data addresses and/or data values passing within the integrated circuit. In such instances, the watchpoint logic may for example be coupled to a bus over which a load store unit of a processor communicates with memory. As another example, the signals being monitored may identify instruction addresses, such as may be
…. Sometimes, watchpoint logic used to monitor instruction addresses is referred to as breakpoint logic, but herein the term "watchpoint" will be used to collectively refer to either a watchpoint or a breakpoint.”. See Figure 6, #530, “Is Counter Accessed non-zero?” That is the addresses in the watchpoint /breakpoint is associated non-zero value generated by Bloom filter)
As per Claim 3: Ford and combining Atamaner, where
Ford further discloses,
3. The data processing apparatus according to claim 1, wherein
the memory addresses comprise locations within a memory at which data access requests are made by the instructions against which a watchpoint is set.
(See in col. 1, lines 61-66, “…The signals being monitored may take a variety of forms, and in one embodiment may identify data addresses and/or data values passing within the integrated circuit. In such instances, the watchpoint logic may for example be coupled to a bus over which a load store unit of a processor communicates with memory.”. )
As per Claim 4: Ford and combining Atamaner, where
Ford further discloses,
4. The data processing apparatus according to claim 1, comprising:
the confirmation circuitry, wherein the confirmation circuitry is configured to store a further data value indicating the plurality of memory addresses.
(See in Fig. 4 with the loop pointed at Book 310, and with box 330 to “Re-Start Integrated” for continued execution, or see col 1, line 55-56, “…to halt execution of the program and pass over control to the debug application..” It is known that execution is at the continued address or debugging is halt at the breakpoint address.)
As per Claim 5: Ford and combining Atamaner, where
Ford discloses the limitations in bold as below:
5. The data processing apparatus according to claim 1, wherein
in response to the [approximate set membership query] being positive, the membership query circuitry is configured to issue a signal to the confirmation circuitry
(Ford: Fig 4, and Col. 14, lines 21-24, “…once the Bloom filter check process has been performed at step 300, then assuming a trigger signal is generated the trigger signal is used to initiate a further
checking operation at step 310 to check for any false hits..”); and
a signal receiving routine at the confirmation circuitry is configured to determine whether the memory address is in the plurality of memory addresses.
(Ford: Fig 4, Box 310 received data from box 300, Fig. 6, box 530 check data from box 520. The “Y” in #530 indicates the address of a range of watchpoint is set by Filter as non-zero)
As addressed in claim 1,
Ford does not explicitly address the limitations of “approximate set membership query”, and
Atamaner addressed the limitations of “approximate set membership query”. See the same rationales addressed in Claim 1 above.
Therefore, it would be obvious to an ordinary of skills in the art before the effective filing of the application to combine the teaching of Atamaner with the Bloom Filter known as storing approximate set membership query and the Bloom filter of Ford with the same reason as addressed in claim 1 above.
As per Claim 6: Ford and combining Atamaner, where
Ford discloses the limitations in bold as below:
6. The data processing apparatus according to claim 1, wherein
at least one of the [membership query circuitry] and the confirmation circuitry is configured to return a negative result indicating that the memory address is not one of the memory addresses in response to the memory address being below a lower limit.
(Ford: Col. 4, lines 13-19, “…By the nature of the Bloom filter, the assumption that the PC value is acceptable is not definitive, and it is possible in fact that the PC value may not have been within the acceptable set. Nevertheless, in the specific implementation described in this article, the view is taken that the probability of false positives is sufficiently low that this does not prove a problem.”.
Thus, return a negative result is in the case the check for false hits is True on Fig. 4 or Counter Accessed is non-zero.)
Ford does not explicitly address the limitations of “membership query circuitry”, and
Atamaner addressed the limitations of “membership query circuitry”. See the same rationales addressed in Claim 1 above.
Therefore, it would be obvious to an ordinary of skills in the art before the effective filing of the application to combine the teaching of Atamaner with the Bloom Filter known as membership query circuitry and the Bloom filter of Ford with the same reason as addressed in claim 1 above.
As per Claim 7: Ford and combining Atamaner, where
Ford discloses the limitations in bold as below:
7. The data processing apparatus according to claim 1, wherein at least one of the [membership query circuitry] and the confirmation circuitry is configured to return a negative result indicating that the memory address is not one of the memory addresses in response to the memory address being above an upper limit.
(Ford: Col. 4, lines 13-19, “…By the nature of the Bloom filter, the assumption that the PC value is acceptable is not definitive, and it is possible in fact that the PC value may not have been within the acceptable set. Nevertheless, in the specific implementation described in this article, the view is taken that the probability of false positives is sufficiently low that this does not prove a problem.”.
Thus, return a negative result is in the case the check for false hits is false on Fig. 4 or Counter Accessed is zero)
Ford does not explicitly address the limitations of “membership query circuitry”, and
Atamaner addressed the limitations of “membership query circuitry”. See the same rationales addressed in Claim 1 above.
Therefore, it would be obvious to an ordinary of skills in the art before the effective filing of the application to combine the teaching of Atamaner with the Bloom Filter known as membership query circuitry and the Bloom filter of Ford with the same reason as addressed in claim 1 above.
As per Claim 8: Ford and combining Atamaner, where
Ford discloses the limitations in bold as below:
8. The data processing apparatus according to claim 1, wherein
at least one of [the membership query circuitry] and the confirmation circuitry is configured to return a negative result indicating that the memory address is not one of the memory addresses based on memory page metadata of the memory address.
(Ford: Col. 4, lines 13-19, as in above claims 6, 7, and see
The incorporation of employing a memory management unit, in col. 2, lines 21-33, “…An alternative approach for monitoring values of particular signals has been to employ a memory management unit (MMU) associated with a particular processing logic to generate trigger signals when particular values are identified. In particular, the MMU has access to page tables identifying
particular attributes associated with pages of memory. For a page of memory associated with a value of interest, for example referenced by a particular address, then the associated entry for that page in the page table can be defined such that when the MMU sees an access to any part of that page, it will generate an abort signal, which can be used as a trigger signal in a similar way to the earlier described trigger signals produced by watchpoint logic..” (emphasis added: “attributes associated with pages of memory” is memory page metadata of the memory address)
Ford does not explicitly address the limitations of “membership query circuitry”, and
Atamaner addressed the limitations of “membership query circuitry”. See the same rationales addressed in Claim 1 above.
Therefore, it would be obvious to an ordinary of skills in the art before the effective filing of the application to combine the teaching of Atamaner with the Bloom Filter known as membership query circuitry and the Bloom filter of Ford with the same reason as addressed in claim 1 above.
As per Claim 9: Incorporated with claim 8 above, Ford and combining Atamaner, where
Ford further discloses the limitations,
9. The data processing apparatus according to claim 8, comprising:
page table circuitry configured to store a plurality of page table entries, wherein of the page table entries is configured to store an indication of whether a corresponding memory page contains one of the memory addresses.
(Ford: Col. 2, lines 21-33, and especially, in 26-33, “For a page of memory associated with a value of interest, for example referenced by a particular address, then the associated entry for that page in the page table can be defined such that when the MMU sees an access to any part of that page, it will generate an abort signal, which can be used as a trigger signal in a similar way to the earlier described trigger signals produced by watchpoint logic..”)
As per Claim 11: Incorporated with claim 8 above, Ford and combining Atamaner, where
Ford further discloses the limitations in bold below:
11. The data processing apparatus according to claim 8, comprising:
update circuitry configured to store an outcome of [one or both of the membership query circuitry] and the confirmation circuitry for one of the page tables in response to execution of instructions corresponding to the one of the page tables.
(Ford: Col. 7, lines 29-36, “…Typically, this may be performed by applying the hash operation to the new value supplied in order to produce an indication of the appropriate update to the configuration data, and then to apply that update to the existing configuration data. Taking the example of a Bloom filter saturating counter vector, this would hence involve incrementing the relevant saturating counter or saturating counters..”: This configuring update is performed within the Bloom Filter.
Col. 2, lines 21-26, “An alternative approach for monitoring values of particular signals has been to employ a memory management unit (MMU) associated with a particular processing logic to generate trigger signals when particular values are identified. In particular, the MMU has access to page tables identifying particular attributes associated with pages of memory..” : Triger Signals are generated by box 310, Fig. 4, or Box 530.
As in Fig.. 4, and Col. 14, lines 34-40, “When the trigger signal is issued by the monitoring logic at
step 300, then typically the integrated circuit will then stall pending the outcome of the debug analysis.”
Note: since claim recites “one or both of the membership query circuitry and the confirmation circuitry”, the limitations of membership query circuitry would not be necessary to function in the claim because the claim recites to require one; therefore, the reference of Ford addresses the limitations of the claim.)
As per Claim 14: Ford and combining Atamaner, where
Ford further discloses the limitations in bold below:
14. The data processing apparatus according to claim 1, comprising:
cache circuitry (See Fig.1 Instruction Cache #30, Data Cache #40), wherein
at least one of the [membership query circuitry] and the confirmation circuitry is configured to determine whether given memory addresses (Incorporated with Caches in Fig. 1 and see Fig.4, and Fig.6, with the rationales address in above claims) whose contents are stored in the cache circuitry are in the plurality of memory addresses (Instruction Cache #30, Data Cache #40), in response to a cache miss (Col. 10, lines 23-29, “…In the event of a cache miss, a linefill process is performed to retrieve a cache line's worth of instruction data into the instruction cache 30 from memory, for example off-chip memory accessed via the system bus 50 and DRAM (Dynamic RAM) interface 70, or
on-chip memory such as the SRAM (Static RAM) memory 80 connected to the system bus 50.”).
Ford does not explicitly address the limitations of “membership query circuitry”, and
Atamaner addressed the limitations of “membership query circuitry”. See the same rationales addressed in Claim 1 above.
Therefore, it would be obvious to an ordinary of skills in the art before the effective filing of the application to combine the teaching of Atamaner with the Bloom Filter known as membership query circuitry and the Bloom filter of Ford with the same reason as addressed in claim 1 above.
As per Claim 15: Incorporated with claim 14 above, Ford and combining Atamaner, where
Ford further discloses the limitations,
15. The data processing apparatus according to claim 14, wherein
the cache circuitry is configured to store an indication of whether the given memory addresses are in the plurality of memory addresses.
(Ford: Fig.1 Instruction Cache #30, Data Cache #40)
As per Claim 16: Ford and combining Atamaner, where
Ford discloses the limitations in bold as below:
16. The data processing apparatus according to claim 1, comprising:
load circuitry configured to replace the data value in the [membership query circuitry] based on a subset of bits of the memory address.
(Ford: Col. 3, lines 10-12, “As an example, it may be desired to detect whenever a load operation loads data from a particular data address..”.
Col. 13, lines 24-32, “…The configuration data can be defined in a variety of ways. In one embodiment, if software having knowledge of the hash operation performed by the hash logic alters the set of values to be monitored, the interface is operable to receive replacement configuration data to be stored in the storage element. Hence, in such embodiments, the monitoring logic merely replaces its configuration data with the new configuration data received via the interface.)
Ford does not explicitly address the limitations of “membership query circuitry”, and
Atamaner addressed the limitations of “membership query circuitry”. See the same rationales addressed in Claim 1 above.
Therefore, it would be obvious to an ordinary of skills in the art before the effective filing of the application to combine the teaching of Atamaner with the Bloom Filter known as membership query circuitry and the Bloom filter of Ford with the same reason as addressed in claim 1 above.
As per claim 17: Claim is directed to a method and recites the limitations having functionality corresponding to the data processing apparatus of claim 1 above. The claim is rejected with the same rationales addressed in claim 1.
As per claim 18: Claim is directed to a non-transitory computer-readable medium and recites the limitations having functionality corresponding to the data processing apparatus of claim 1 above. The claim is rejected with the same rationales addressed in claim 1.
As per claim 19:
19. A system comprising:
the data processing apparatus of claim 1, implemented in at least one
packaged chip;
at least one system component; and
a board, wherein
the at least one packaged chip and the at least one system component are
assembled on the board.
Above limitations recite the standard components in a circuit board in a computer to implement the claim 1 that is addressed by Ford and in view of Atamaner, and the limitations read on the such as an implementation in Ford’s Fig. 1.
Therefore, Claim recites the limitations having functionality corresponding to the data processing apparatus of claim 1. The claim is rejected with the same rationales addressed in claim 1.
As per claim 20:
20. A chip-containing product comprising the system of claim 19, wherein
the system is assembled on a further board with at least one other product
component.
Above limitations recite chip components in a standard circuit board in a computer , and the chip product is formed within the system and in Ford’s Fig. 1.
Therefore, Claim recites the limitations having functionality corresponding to the data processing apparatus of claim 1. The claim is rejected with the same rationales addressed in claim 1.
Allowable Subject Matter
Claims 10, 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ted T Vo whose telephone number is (571)272-3706. The examiner can normally be reached 8am-4:30pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wei Y Mui can be reached at (571) 272-3708. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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TTV
March 20, 2026
/Ted T. Vo/
Primary Examiner, Art Unit 2191