DETAILED ACTION
The communication is in response to the application filed on 04/19/2024 in which claims 1-17 are pending in the application. Claims 1 and 8 are independent form.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. TW113105853, filed on 02/19/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7-9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Rao et al. (US 20140049551 A1), in view of Orschel et al. (US 20140189273)
As per claim 1 Rao discloses:
A method for processing data based on shared virtual memory, applied to a system comprising a central processing unit and a graphics processing unit, the central processing unit and the graphics processing unit configured to share a virtual memory record in a storage medium, wherein the method comprises: [0001] “The present invention relates generally to the shared virtual memory between a central processing unit (CPU) and a graphics processing unit (GPU) within a computing system.”
configuring the central processing unit to assign a task to be executed by the graphics processing unit, wherein data required for the task is associated with the virtual memory record;
[0012] “By offloading a portion of the computational tasks traditionally performed by the CPU of a computing device to the GPU of a computing device…. offload tasks to the GPU, data may be transferred between the physical memory of the CPU to the physical memory of the GPU.” [0030] “A memory management unit (MMU) 126 may be used to manage access to data that is stored within the surface 122.…. Accordingly, the MMU 126 includes a CPU page table 128 and a GPU page table 130.”
Rao does not explicitly disclose “configuring the central processing unit to anchor the data required for the task during the task executed by the graphics processing unit.”
However, Orschel discloses “configuring the central processing unit to anchor the data required for the task during the task executed by the graphics processing unit.” [0023] “Unless previously used private super pages have become ready for re-use, a map ahead thread, having high priority, acquires private (non-file-mapped) super pages of at least two native pages, for overlapping and locks them so they cannot be swapped out by the operating system.” [0053] “Because the pages are not mapped to a file and are locked (not swappable) memory locations, they can be written to in real-time continuously with no delay or interruption.” [0061] “The term processor, as used herein, refers to central processing units, microprocessors, microcontrollers, reduced instruction set circuits (RISC), application specific integrated circuits (ASIC), logic circuits, and any other circuit or processor capable of executing the functions described herein”
Both Rao and Orschel are in the similar field of endeavor as they are both in tasks processing and, therefore, are combinable/modifiable.
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to modify the teaching of Rao, with the teachings of Orschel, to configure the central processing unit to anchor the data required for the task executed by the graphic processing unit.
Motivation to combine would be to improve the utilization of the central processing unit and the graphic processing unit to using a command with high priority to prevent the required data that is being assign from the central processing unit to the graphic processing unit to lock/pin the data from swapping or switching during being process by the graphic processing unit.
As per claim 2, Rao and Orschel disclose the method of claim 1 detailed above.
Orschel further disclose “configuring the central processing unit to set an area related to the data required for the task in a physical memory associated with the virtual memory record to a removal-prohibited-enable state before the graphics processing unit begins executing the task and until the execution of the task is completed to configure the central processing unit to set the area being removal-prohibited in the physical memory associated with the virtual memory record to a removal-prohibited-disable state.” [0023] “Unless previously used private super pages have become ready for re-use, a map ahead thread, having high priority, acquires private (non-file-mapped) super pages of at least two native pages, for overlapping and locks them so they cannot be swapped out by the operating system. These pages are used by real-time threads, writing data at full resolution with increasing index.” [0048] “data-logging system 600 includes a map-ahead thread 602 configured to acquire blocks of private memory 604 and lock in memory…. also includes a master thread 606 configured to write data to the file-mapped blocks of memory, in real-time and in full resolution, the data is acquired during operation of a machine generating the data, the machine including a controller including a processor communicatively coupled to a memory.” [0046] “"lock" or "locking" means preventing memory pages from being swapped to hard disk by the operating system.” [0049] “Write-behind thread 608 is configured to acquire file-mapped blocks of memory, copy the content of inactive blocks of private memory 604 to the file-mapped blocks of memory and release the file-mapped blocks of memory after copying the data from the private blocks to the file-mapped blocks.” [0053] “Because the pages are not mapped to a file and are locked (not swappable) memory locations, they can be written to in real-time continuously with no delay or interruption.”
As per claim 7 Rao and Orschel disclose the method of claim 1 detailed above.
Rao further discloses “wherein the virtual memory record is a page table.” [0030] “Accordingly, the MMU 126 includes a CPU page table 128 and a GPU page table 130.”
As per claim 8, it has similar limitation as claim 1, and therefore rejected using the same rationale.
As per claim 9, it has similar limitation as claim 2, and therefore rejected under the same rationale.
As per claim 17, it has similar limitation as claim 7, and therefore rejected using the same rationale.
Claims 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Rao et al. (US20140049551 A1), in view of Orschel et al. (US 20140189273), in of view Belkar et al. (US20230014415 A1).
As per claim 3 Rao and Orschel disclose a method of claim 2 detailed above.
Rao and Orschel do not explicitly disclose
“configuring the central processing unit to prefetch a plurality of pages associated with the data to the physical memory and to prohibit the pages including the data required for the task from being removed from the physical memory before the graphics processing unit begins executing the task.”
However, Belkar does disclose “configuring the central processing unit to prefetch a plurality of pages associated with the data to the physical memory and to prohibit the pages including the data required for the task from being removed from the physical memory before the graphics processing unit begins executing the task.” [0003] “The memory pinning is a technique used by the typical operating systems to prevent a memory subsystem from moving physical pages from one location to another, and possibly alter a virtual address (VA)-to-a physical address (PA) translation. The memory pinning also prevents memory pages of the memory subsystem moving from random access memory (RAM) into a backing store or a swap area (a process known as “swapping out”).” [0008] “The requesting device of the present disclosure enables prefetching of required memory pages which may currently be not allocated or swapped out in order to reduce a delay (or a complete transaction latency). The transmission of the message comprising the prefetch operation (or a prefetch hint) before the request…. enables the responding device to prefetch the required memory pages (as per need) ahead of time and makes the preparations to accept the request” [0030] “message transmitter module when executed causes the requesting device to transmit the message comprising the prefetch operation to the responding device. The prefetch operation includes prefetching of a required memory area into the memory (e.g. a CPU's cache memory or an internal memory) of the responding device which enables the fast data communication.”
Rao, Orschel and Belkar are in the similar field of endeavor as they are both in data processing and, therefore, are combinable/modifiable.
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to modify the teaching of Rao, with the teachings of Orschel, and the teaching of Belkar to configured the central processing unit to prefetch a plurality of pages associated with the data to the physical memory, and to prohibit the pages including the data required for the task from being removed from the physical memory.
Motivation to combine would be to improve the system by reducing delays and page faults that could occurs if the central processing unit lock the required task.
As per claim 10, it has similar limitation as claim 3, and therefore rejected under the same rationale.
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Rao et al. (US20140049551 A1), in view of Orschel et al. (US 20140189273), in view of Compton et al. (US 20240211334 A1)
As per claim 4, Rao and Orschel disclose a method of claim 2 detailed above.
Orschel further discloses “configuring the central processing unit to determine whether the data is available in the physical memory;
in response to the central processing unit determining the data being available in the physical memory, configuring the central processing unit to set the area related to the data required for the task in the physical memory to the removal-prohibited-enable state [0048] “data-logging system 600 includes a map-ahead thread 602 configured to acquire blocks of private memory 604 and lock in memory” [0049] “Map-ahead thread 602 is configured to acquire new blocks of private memory 604 and lock them in memory when the amount of available unused private blocks is outside a predetermined threshold range. “[0053] “Because the pages are not mapped to a file and are locked (not swappable) memory locations, they can be written to in real-time continuously with no delay or interruption.”;
….and to set the area related to the data required for the task in the physical memory to the removal-prohibited-enable state. [0048] “data-logging system 600 includes a map-ahead thread 602 configured to acquire blocks of private memory 604 and lock in memory” [0049] “Map-ahead thread 602 is configured to acquire new blocks of private memory 604 and lock them in memory when the amount of available unused private blocks is outside a predetermined threshold range. “[0053] “Because the pages are not mapped to a file and are locked (not swappable) memory locations, they can be written to in real-time continuously with no delay or interruption.”
Rao in view Orschel do not explicitly disclose “in response to the central processing unit determining the data being unavailable in the physical memory, configuring the central processing unit to store the data in the physical memory….”
However, Compton discloses “in response to the central processing unit determining the data being unavailable in the physical memory, configuring the central processing unit to store the data in the physical memory….”
[0014] “In some embodiments, the kernel can include a virtual memory manager component configured to maintain a subset of secondary storage space on the storage 170 for temporarily storing content that the physical memory 160 is currently insufficient or otherwise unavailable to store.”
Rao, Orschel and Compton are in the similar field of endeavor as they are both in data processing and, therefore, are combinable/modifiable.
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to modify the teaching of Rao, with the teachings of Orschel, and with the teachings of Compton to determine the data being unavailable in the physical memory, configuring the central processing unit to store the data in the physical memory [0014 Compton] and to set the area related to the data required for the task in the physical memory to the removal-prohibited-enable state [0048 Orschel].
Motivation to combine would be to improve the system by preventing pages from being swapped out when data is unavailable in the physical memory.
As per claim 11, it has similar limitation as claim 4, and therefore is rejected under the same rationale.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Rao et al. (US20140049551 A1), in view of Orschel et al. (US 20140189273), Kim et al. (US20140304712 A1).
As per claim 5, Rao and Orschel disclose the method of claim 1 detailed above.
Rao and Orschel do not explicitly disclose “configuring the central processing unit to set the task to be a single task or to set the task to comprise a plurality of batch-operating subtasks in a batch operation.”
However, Kim discloses “configuring the central processing unit to set the task to be a single task or to set the task to comprise a plurality of batch-operating subtasks in a batch operation.” [0080] “If it is determined in operation 805 that task combination is needed, the system may combine an executing plurality tasks to one task based on a workload and a CPU situation in operation”
Rao, Orschel and Kim are in the similar field of endeavor as they are both in data processing and, therefore, are combinable/modifiable.
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to modify the teaching of Rao, with the teachings of Orschel and with the teachings of Kim to configure the central processing unit to set the task to comprise a plurality of batch-operating subtasks in a batch operation.
Motivation to combine would be to improve the utilization of the central processing unit by reducing task.
As per claim 12, it has similar limitation as claim, and therefore it rejected using the same rationale.
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Rao et al. (US 20140049551 A1), in view of Orschel et al. (US 20140189273), in view of Thaler et al. (US 5983329 A)
As per claim 6, Rao and Orschel disclose a method of claim 1 detailed above.
Rao and Orschel do not explicitly disclose “…. configuring the central processing unit to set a locked range of a physical memory associated with the virtual memory record to be 35% to 65% of an access space of the physical memory before the graphics processing unit begins executing the task.”
However, Thaler discloses “…. configuring the central processing unit to set a locked range of a physical memory associated with the virtual memory record to be 35% to 65% of an access space of the physical memory before the graphics processing unit begins executing the task.” [col 3 lines 60-67 col 4 lines 1-5] “Each of these processes represent a process or program running on the CPU within the computer system. Each process may also have associated with it any number of threads. Each of these processes also represents a unique virtual address space that may have certain regions of virtual memory locked at a given time. These regions of virtual memory may be temporarily locked in physical memory because the process needs access to the information (data, program instructions) contained in the virtual memory. The regions of virtual memory that are locked by the process may each be represented conceptually by a data structure called a range lock. Each process may have a corresponding set of range locks 20 as shown.
Rao, Orschel and Thaler are in the same field of endeavor as they are both in allocating within memory and, therefore, are combinable/modifiable.
Under BRI Thaler does not explicitly state a 35% to 60% of access space however Thaler discloses “set of range lock” which can encompass the percentage that is stated. (See MPEP 2144.05)
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to modify the teaching of Rao, with the teachings of Orschel and with the teachings of Thaler to configured central processing unit to set a locked range of a physical memory associated with the virtual memory record to have a set access space of the physical memory.
Motivation to combine would be to improving the system by enhancing the performance within memory space to be faster and reduce time of processing data.
As per claim 13, it has similar limitation as claim 6 and therefore is rejected under the same rationale.
Claim 14 are rejected under 35 U.S.C. 103 as being unpatentable over Rao et al. (US20140049551 A1), in view of Orschel et al. (US 20140189273), in view of Mishra et al. (US20250156208 A1).
As per claim 14 Rao and Orschel disclose a system of claim 8 detailed above.
Rao and Orschel do not explicitly disclose “wherein the central processing unit is a RISC-V central processing unit generated by a virtual machine simulation.”
However, Mishra discloses “wherein the central processing unit is a RISC-V central processing unit generated by a virtual machine simulation.” [0017] “Processor and/or system-on-a-chip (SoC) emulation platforms (collectively referred to hereinafter as SoC emulation platforms) are virtualization tools configured to provide a user with a mechanism for simulating hardware platforms, such as central processing units (CPUs)….” [0057] “In some examples, each emulation may be of a processing core (Cortex-A, Cortex-M, RISCV, etc.) different from other emulations. For example, each emulation may include its own OS, firmware, application software, etc., for example, as illustrated in the VMs 116 of FIG. 1.”
Rao, Orschel, and Mishra are in the similar field of endeavor as they are both in data processing and, therefore, are combinable/modifiable.
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to modify the teaching of Rao, with the teachings of Orschel and with the teachings of Mishra that central processing unit is a RISC-V that is generated by the virtual machine simulation.
Motivation to combine would be to improve the system by fully controlling and customizing the RISC-V that is implement within the central processing unit which is then emulated by a virtual machine.
Claim 15 are rejected under 35 U.S.C. 103 as being unpatentable over Rao et al. (US20140049551 A1), in view of Orschel et al. (US 20140189273), in view of Mishra et al. (US20250156208 A1), in view of Wiegert et al. (US 20220414968 A1), in view of Borlick et (US 9753773 B1)
As per claim 15, Rao, Orschel and Mishra disclose the system of claim 14 detailed above.
Rao, Orschel and Mishra do not explicitly disclose:
“wherein the graphics processing unit comprises a task dispatcher, a page fault controller, and a plurality of streaming processing cores;
the plurality of streaming processing cores are coupled to the task dispatcher and the page fault controller;
the task dispatcher is configured to receive the task and to dispatch the task to one of the plurality of streaming processing cores according to a working status of the plurality of streaming processing cores;
the page fault controller is configured to integrate page-fault-exception information from the plurality of streaming processing cores and to issue a page-fault-exception interrupt to the virtual machine;
and the plurality of streaming processing cores are configured to process the task dispatched by the task dispatcher.”
However, Wiegert discloses
wherein the graphics processing unit comprises a task dispatcher, a page fault controller, and a plurality of streaming processing cores;
the plurality of streaming processing cores are coupled to the task dispatcher and the page fault controller; [0402] “In some implementations, the page fault exception feature is enabled in response to a debugger application being attached to the graphics processor. At kernel dispatch 2820, the page fault exception enable value is set 2825 in a control register (CR) corresponding to one or more of the threads of the EU 2801.”
the page fault controller is configured to integrate page-fault-exception information from the plurality of streaming processing cores and to issue a page-fault-exception interrupt to the virtual machine; [0406] FIG. 29 is a block diagram illustrating a graphics processing system 2900 to enable page fault exceptions, in accordance with implementations herein. Graphics processing system 2900 may illustrate a portion of a graphics processor and is shown to include a thread dispatcher 2930 and one or more EUs 2940…. the executing of a first instruction after being dispatched from thread dispatcher 2930 to a processing resource…. stream processors, streaming multiprocessor (SM)…” (See Fig 29) [0416] “…Theses control registers 3220 can be used to communicate the memory exception details to the thread. The exception handling routine can then read the exception details from the control registers 3220, including the debug register 3220-5, and send these details to the debugger application (e.g., executing on the host).” [0129] A VM can include an operating system (OS) or application environment that is installed on software, which imitates dedicated hardware. The end user has the same experience on a virtual machine as they would have on dedicated hardware. Specialized software, called a hypervisor, emulates the PC client or server's CPU…”
Rao, Orschel, Mishra and Wiegert are in the similar field of endeavor as they are both in data processing and, therefore, are combinable/modifiable.
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to modify the teaching of Rao, with the teachings of Orschel, with the teachings of Mishra, and with the teachings of Wiegert, to have a graphic processing unit to comprise a task dispatcher, page fault controller, and plurality of streaming processing cores, which the plurality of streaming processing cores are coupled to a task dispatcher and page fault controller, and which the page controller to receive information the streams of processor to send an interrupt to the virtual machine.
Motivation to combine would be to improve the system by optimizing the performance of workloads.
Rao in view of Orschel, Mishra and Wiegert do not explicitly disclose:
“the task dispatcher is configured to receive the task and to dispatch the task to one of the plurality of streaming processing cores according to a working status of the plurality of streaming processing cores;
and the plurality of streaming processing cores are configured to process the task dispatched by the task dispatcher. “
However, Borlick discloses “the task dispatcher is configured to receive the task and to dispatch the task to one of the plurality of streaming processing cores according to a working status of the plurality of streaming processing cores;” [col 1 lines 55-59] “which select a plurality of processor cores of a multi-processor core system, as available to receive a dispatched task, to define a set of available processor cores in which each processor core of the set of available processor cores is selected as available to receive a dispatched task.”
“the plurality of streaming processing cores are configured to process the task dispatched by the task dispatcher.” [col 6 lines 22-24] “…tasks are dispatched to processor cores of the set of available of processor cores for processing by processor cores of the set of available processor…”
Rao, Orschel, Mishra, Wiegert and Borlick are in the similar field of endeavor as they are both in data processing and, therefore, are combinable/modifiable.
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to modify the teaching of Rao, with the teachings of Orschel, with the teachings of Mishra, with the teachings of Wiegert, and with the teachings of Borlick to have graphic processing unit the comprise a task dispatcher to assign a task according to the working status of the set of the processors, and then to have the set of the processors to task that was assign from the task dispatcher.
Motivation to combine would be to improve the system by optimizing the load balances with the plurality streaming processor before assign a task which reduce any type of restriction, or congestion.
Claim 16 are rejected under 35 U.S.C. 103 as being unpatentable over Rao et al. (US20140049551 A1), in view of Orschel et al. (US 20140189273), in view of Mishra et al. (US20250156208 A1), in view of Wiegert et al. (US 20220414968 A1), in view of Borlick et (US 9753773 B1), in view of Verm et al. (US 20080183931 A1)
As per claim 16, Rao, Orschel, Mishra, Wiegert and Borlick disclose a system in claim 15 detailed above.
Rao, Orschel, Mishra, Wiegert and Borlick do not disclose “a virtual address and a streaming processing core number associated with a page fault exception occurring in one of the plurality of streaming processing cores.”
However, Verm discloses “a virtual address and a streaming processing core number associated with a page fault exception occurring in one of the plurality of streaming processing cores.” [0001] “The present invention relates in general to virtual memory shared between multiple processors…” [0024] “…. problems caused by faults resulting from an attempt to access an invalid virtual address by a digital signal processor (DSP) in a multiprocessor system. When a page fault (also referred to herein as a memory management fault or fault) is caused by the DSP attempting to access an invalid virtual address in shared memory… for debugging following a page fault which causes the DSP to crash…” [0025] “The microprocessor can install a microprocessor interrupt handler to catch any interrupt generated by the DSP MMU in response to a page fault interrupt due to an invalid virtual address.”
Under the BRI, Verm disclose a streaming processing core that is refer as “multiprocessor system” however in the claim it states “number associated with a page fault exception occurring in one of the plurality of streaming processing cores” which just reads into an error caused by page fault, which lead the streaming processing core to fail.
Rao, Orschel, Mishra, Wiegert, Borlick and Verm are in the similar field of endeavor as they are both in virtual memory and, therefore, are combinable/modifiable.
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing date of the claimed invention to modify the teaching of Rao, with the teachings of Orschel, with the teachings of Mishra, with the teachings of Wiegert, with the teachings of Borlick, and with the teachings of Verm to have the page-fault-exception information to include a virtual address and a streaming processing core number associated with a page fault exception occurring in one of the plurality of streaming processing cores.
Motivation to combine would be to be to improve the graphics processing unit by handling an error when the streaming processing core fail based on the page faults.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
FARGO; Farah E. (US 20200233814 A1) disclose allocate a contiguous physical memory region to a virtual address range by specifying a custom range sizes that are larger or smaller than the normal general page sizes.
KOTRA; JAGADISH B. (US 20220206817 A1) discloses an offload instruction for an operation to be offloaded is processed and a lock is placed on a memory address associated with the offload instruction.
Amaro Ramirez; Emmanuel (US 20220334774 A1) discloses are various approaches for decreasing the latency involved in reading pages from swap devices. These approaches can include setting a first queue in the plurality of queues as a highest priority queue and a second queue in the plurality of queues as a low priority queue.
Ponnuswamy; Basker (US 20090228743 A1) disclose a page fault/TLB miss handler to store page fault data, associated with the page fault, in a second data structure in response to a page fault; and a dump manager to store, in response to an event, memory access data derived from the physical memory according to at least a portion of the page fault data.
Lee; Jaejin (US 20140040563 A1) disclose a shared virtual memory management apparatus allocates a physical memory page for the cores to change data in the allocated physical memory page.
Stillwell; Paul M. JR (US 20060107020 A1) disclose sharing data in a user virtual address range with a kernel virtual address range.
Jiang; Xiaowei (US 20130311738 A1) disclose The CPU core comprises a pipeline having a translation look aside buffer. The CPU core comprising logic circuitry to set a lock bit in attribute data of an entry within the translation look-aside buffer entry to lock a page of memory reserved for the accelerator.
Kumar; Derek R. (US 9507726 B2) disclose manages virtual memory for a graphics processing unit that includes a central processing unit.
Saxena; Paritosh (US 20160117497 A1) disclose the computing platform including a central processing unit and a graphics processing unit; and an offloader to determine whether the central processing unit or the graphics processing unit is to execute the security task; and when the graphics processing unit is to execute the security task, offload the security task to the graphics processing unit for execution.
Garbett; David Thomas (US 20250173198 A1) disclose reduce, latencies introduced or incurred by a (host) processor e.g. a central processing unit (CPU), during virtualisation, in which virtual machines that are operable to execute on the (host) processor are scheduled or assigned to the graphics processor in a time-slice manner.
DULUK, JR.; Jerome F. (US 20210073025 A1) disclose executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions.
RAMADOSS; MURALI (US 20200293456 A1) disclose an apparatus comprises a processor to receive a virtual address that triggered a page fault for a compute process, check a virtual memory space for a virtual memory allocation for the compute process that triggered the page fault.
Wilt; Nicholas Patrick Rochester (US 8395631 B1) disclose to allocate a memory buffer in the system memory of a computer system that is shared among a plurality of graphics processing units (GPUs).
Mukherjee; Anupam (US 20200264786 A1) discloses a locked memory pool can ensure that more important data items remain available even when they are the least recently used.
Herr, Brian D. (US 20030101324 A1) discloses a pinned kernel memory pool from which memory buffers are allocated to time critical processing tasks.
LEE; Bum Sik (US 20150135020 A1) disclose measuring the memory usage used only in a swap memory from an active virtual memory.
Shimizu; Takashi (US20160267018 A1) disclose reducing processing time of a memory access instruction by efficiently arranging and using areas in a cache memory.
Raisch; Christoph (US 20190310947 A1) disclose transferring data between a computer program executed by a processor and an input/output device using a memory accessible by the computer program.
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/A.A./Examiner, Art Unit 2198
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
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