Detailed action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office action is in response to the application filed April 19, 2024.
2. Claims 1-20 are pending and has been examined.
Drawings
3. Drawings submitted on 04/19/2024 are acceptable.
Claim objection
4. Claim 19 is objected because of the following informalities:
Claim recites “a converter output voltage” in line 6 should be “the converter output voltage”.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,8, 12 and 14-15 are rejected under 35 U.S.C. 102(a)(1) (a)(2 ) as being anticipated by Houston “US 20140368174”.
In re to claim 1, Houston discloses a circuit (Figs. 1-13 shows a power supply including a regulator) comprising: an input terminal (Fig.13 shows Z1 input terminal is coupled to Vo) is configured to receive a converter output voltage (an output node 204) ; a reference voltage circuit having an output (voltage source 1303 output reference voltage VREF);
a comparator (1301) having a first input (negative terminal) coupled to the input terminal (Vout is coupled to output node 204) , a second input (positive terminal) coupled to the output of the reference voltage circuit (Vref), and
an overvoltage output (VCOMP is provided to an input of the modulator 205 and the modulator 205 develops the pulse control signal or PWM signal, see prag.0070. When Vout is exceeded Vref, which indicates an overvoltage fault [equivalent to COMP]. Examiner noted that COMP is the same as PWM signal );
a delay circuit (combination of 1-shot device 1333 and a delay block 1335) having an input coupled to the overvoltage output (PWM signal is provided to 1-shot 1333, see prag.0081) , and
a delayed overvoltage output (output voltage from delay block 1335)
a conduction mode control circuit (a combination of an AND gate 1337 and 1209) having a first input coupled to the overvoltage output (AND gate 1337 is coupled to PWM signal) , a second input coupled to the delayed overvoltage output (output from DLY 1335 is provided to the other input of the AND gate 1337) , and a mode output (SB signal) ; and
a switching converter controller (Fig. 2 shows a controller 201) having a conduction mode input coupled to the mode output (AND gate 1321 coupled to SE signal)
In re to claim 8, Houston discloses a circuit a circuit (Figs. 1-13) comprising: a switching converter controller (Fig. 2 shows controller 201) configured to control switching of a switch mode converter circuit (Figs. 2 and 13 shows a DC-DC buck) ;
a comparator (1301) configured to compare a switch mode converter output voltage (Vout) to an overvoltage threshold voltage (Vref) , and provide an overvoltage signal (VCOMP) indicating that the switch mode converter output voltage is greater than the overvoltage threshold voltage (VCOMP is provided to an input of the modulator 205 and the modulator 205 develops the pulse control signal or PWM signal, see prag.0070. When Vout is exceeded Vref, which indicates an overvoltage fault [equivalent to COMP]. Examiner noted that COMP is the same as PWM signal ) ;
a delay circuit (combination of 1-shot device 1333 and a delay block 1335) coupled to the comparator (MOD 205 is coupled to 1-shot 1333), the delay circuit configured to delay the overvoltage signal (output signal from DLY 13335 is delayed PWM signal), and provide a delayed overvoltage signal (output from DLY 1335 is provided to the other input of the AND gate 1337); and
a conduction mode control circuit (a combination of an AND gate 1337 and 1209) having inputs coupled to the comparator and the delay circuit (an AND gate 1337 is coupled to PWM signal and DLY 1335 output ), and a mode output (SB signal) coupled to the switching converter controller (201), the conduction mode control circuit configured to cause the switching converter controller to transition from operation in a discontinuous conduction mode to a continuous conduction mode responsive to the overvoltage signal and the delayed overvoltage signal (see Figs. 6-8, parag. 0045-0050)
In re to claim 12, Houston discloses a circuit (Figs. 1-13) wherein the delay circuit (1335) is configured to set the delayed overvoltage signal to an overvoltage state responsive to the overvoltage signal indicating (PWM signal) that the switch mode converter output voltage is greater than the overvoltage threshold voltage for a selected transient suppression time (an error amplifier 1301 is comparing the output voltage and Vref. Examiner noted that the error VCOMP is an indication of when output voltage is exceeded the reference voltage which indicates an overvoltage fault and potentially damaged the load .Therefore, the delay circuit is configured to delay/suppress the PWM signal)
In re to claim 14, Houston discloses a circuit a system (Figs. 1-13 shows a power supply including a regulator) comprising: a power source (Fig. 2 and 13 shows DC-DC buck converter comprises power source Vin. Examiner noted that it is understood Vin is DC source) having an output ( DC source output (Vin) is coupled to switch Q1) ;
a switch mode converter circuit having an input coupled to the output of the power source (Figs. 2 and 13 shows a DC-DC buck converter configured to receive output from power source Vin); and
an advanced driver assistance system (buffer/driver 1305 and 1307) and having an input coupled to the output of the switch mode converter circuit (see Fig.13) , the switch mode converter circuit including:
a reference voltage circuit having an output (voltage source 1303 output reference voltage VREF);
a comparator (1301) having a first input (negative terminal) coupled to the output of the switch mode converter circuit (Vout which is coupled to output node 204),
a second input (positive terminal) coupled to the output of the reference voltage circuit (Vref),, and
an overvoltage output (VCOMP is provided to an input of the modulator 205 and the modulator 205 develops the pulse control signal or PWM signal, see prag.0070. When Vout is exceeded Vref, which indicates an overvoltage fault [equivalent to COMP]. Examiner noted that COMP is the same as PWM signal );
a delay circuit (combination of 1-shot device 1333 and a delay block 1335)
having an input coupled to the overvoltage output (PWM signal is provided to 1-shot 1333, see prag.0081), and
a delayed overvoltage output (output voltage from delay block 1335) ;
a conduction mode control circuit (a combination of an AND gate 1337 and 1209) having a first input coupled to the overvoltage output (AND gate 1337 is coupled to PWM signal), a second input coupled to the delayed overvoltage output (output from DLY 1335 is provided to the other input of the AND gate 1337), and a mode output (SB signal); and
a switching converter controller (Fig. 2 shows a controller 201) having a continuous conduction mode (CCM) input coupled to the mode output (AND gate 1321 coupled to SE signal).
In re to claim 15, Houston discloses a circuit (Figs. 1-13) , wherein the conduction mode control circuit is configured to cause the switching converter controller (201) to operate in the CCM responsive (see Figs. 6-8) to an overvoltage signal provided at the overvoltage output and a delayed overvoltage signal provided at the delayed overvoltage output (an error amplifier 1301 is comparing the output voltage and Vref. Examiner noted that the error VCOMP is an indication of when output voltage is exceeded the reference voltage which indicates an overvoltage fault and potentially damaged the load . Therefore, the delay circuit is configured to delay the delay/suppress the overvoltage incident.)
Allowable Subject Matter
6. Claims 2-7, 9-13 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 , the prior art of record fails to disclose or suggest the circuit including the limitation of “the conduction mode control circuit is configured to provide a CCM control signal at the mode output; and the conduction mode control circuit is configured to set the CCM control signal to a first state responsive to an overvoltage signal at the overvoltage output having the first state; and the switching converter controller is configured to operate in a continuous conduction mode responsive to the CCM control signal in the first state.”
Claim 9, the prior art of record fails to disclose or suggest the circuit including the limitation of “ the conduction mode control circuit is configured to provide a CCM control signal at the mode output; and the conduction mode control circuit is configured to set the CCM control signal to a CCM state responsive to the overvoltage signal indicating that the switch mode converter output voltage is greater than the overvoltage threshold voltage; and the switching converter controller is configured to operate in a continuous conduction mode responsive to the CCM control signal in the CCM state. ”
Claim 14, the prior art of record fails to disclose or suggest the system including the limitation of “ the conduction mode control circuit is configured to provide a CCM control signal at the mode output; and the conduction mode control circuit is configured to set the CCM control signal to a first state responsive to an overvoltage signal at the overvoltage output having the first state, and a delayed overvoltage signal at the delayed overvoltage output have a second state; and the switching converter controller is configured to operate in the CCM responsive to the CCM control signal in the first state. ”
Claims 3-7 depend from claim 2 , thus are also objected because of their dependency.
Claims 10-13 depend from claim 9 , thus are also objected because of their dependency.
Claims 17-20 depend from claim 16 , thus are also objected because of their dependency.
Conclusion
7. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang “20190356223” the invention relates to a power circuit, and more particularly, relates to a dc-dc converting circuit and a method for controlling the same.
Chen “9647540” the invention relates to a power regulating technology, and more particularly, to a timing generator and a timing generation method for a power converter.
Nercer”9929653” the present invention relates to a multi-level buck converter, and more particularly to a multi-level buck converter with multiple control loops for regulating the output voltage while also regulating the flying capacitor voltage.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tran, Thienvu Vu can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838