Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 4 is objected to because of the following informalities:
In claim 4, lines 1-2, “the first control signal” should read as --a first control signal--.
In claim 4, line 2, “the second control signal” should read as --a second control signal--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5-9, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Koyama et al. (US 5384501 A) in view of Zanchi et al. (US 20150206600 A1), hereafter referred to as “Koyama” and “Zanchi”, respectively.
Regarding claim 1, 2, 5- 9, and 13 in the embodiment of Fig. 17, Koyama discloses:
A varactor driver for a varactor diode load (column 3, lines 24-41, the time constant of the integration circuit can be controlled using a varactor diode as a load capacitance (e.g. the capacitor 17 used as a load in Figs. 1, 2, 5-13, 25, 26, 29-31, 34, 35 and Fig. 17 where capacitor C2 can be the load as taught for Fig. 14 in column 11 lines 11-26 and column 10 lines 21-23) as per claim 2), the varactor driver comprising:
a first switch (Fig. 9, FETs are in parallel with Resistor R1 to Rn and used as switches, per column 6 lines 30-39) controlled by a control signal (control voltage Vc1-Vcn);
a second switch (Fig. 9, FET in parallel to Resistor R2) controlled by the control signal;
an operational amplifier (Fig. 15, transistors 25 and 26 constitute emitter followers as buffers per column 10 lines 33-42, a variable-Gm operational amplifier is also to be applied to a filter (e.g. Fig. 17, unbalanced active filter voltage controlled current sources 41 and 42) as per claim 13), wherein the operational amplifier is configured to be a unity gain buffer wherein the unity gain buffer comprises a non-inverting input terminal, an inverting input terminal, an output terminal (as shown in Fig. 17, unbalanced voltage controlled current source 42 and shown as a transconductance amplifier as taught in (e.g. Fig. 14, column 10 lines 13-16)), a power supply terminal connected to a power source (analogously in Fig. 15 transistors 25 and 26 shown to be connected to power source Vcc), and a ground terminal connected to ground (Fig. 15, bottom terminal is connected to GND, per claims 5 and 8), the non-inverting input terminal connects to the capacitor (as shown in Fig. 17, per claim 6), the output terminal connects to the varactor diode (Fig. 17, output of amplifier 42 is connected to capacitor C2, per claim 7), and wherein the operational amplifier is configured to be the unity gain buffer by connecting the inverting input terminal to the output terminal (as shown in Fig. 17, per claim 9); and
a capacitor (Fig. 17, capacitor 43) configured to operate in the holding mode to provide a holding- voltage as an output voltage (column 11, lines 39-46 capacitor 43 for constituting an integration circuit is connected to the output terminal OUT certain cases).
However, Koyama is silent in teaching, the varactor driver is CMOS based being configured to operate in a tracking mode when the first switch and the second switch are tuned on and to operate in a holding mode when the first switch and the second switch are tuned off and the operational amplifier is connected with the second switch in parallel and the capacitor configured to operate in the holding mode to provide a holding-voltage, wherein the operational amplifier is constructed using CMOS technology.
Zanchi teaches:
the varactor driver being configured to operate in a tracking mode when the first switch and the second switch are tuned on and to operate in a holding mode when the first switch and the second switch are tuned off (paragraph [0004], Sample/Hold (S/H) circuit including switches 104 and 106, capacitor Cs, and operational amplifier 108 configured as a buffer amplifier, furthermore coefficients can exceed 1000’s of ppm/V for capacitor structures offering highest densities, such as M-O-S varactor implementations); and
the operational amplifier is connected with the second switch in parallel (switch 310 is shown in parallel to operational amplifier 308 in Fig. 3, as an addition circuit detail to Fig. 2); and
the capacitor configured to operate in the holding mode to provide a holding-voltage (capacitor Cs is part of a switched-capacitor Sample/Hold (S/H) circuit per paragraph [0004] lines 7-10).
It would have been obvious to modify the switches in Koyama with the switch configuration, as taught by Zanchi (Figs. 2 and 3), to be part of a sampling capacitor circuit for an input current (per paragraph [0017]), thereby suggesting the obviousness of such a combination. Furthermore, it would be obvious to have a switch in parallel with the operational amplifier, such as the switch taught by Zanchi (Fig. 3), as part of the sample and hold circuit in lieu of having a switch before the operational amplifier (per paragraph [0019]), thereby suggesting the obviousness of such a modification. It would be further obvious to modify the capacitor, such as the capacitor taught by Koyama (Fig. 17, C1), to hold a charge and transfer it to a lower-density, linear capacitor and function as a sampling capacitor (per paragraphs [0017]-[0018]), thereby suggesting the obviousness of such a modification. It would further be obvious to for the varactor driver circuit, wherein the operational amplifier is constructed, as taught by Koyama to be CMOS based, as taught in Koyama (column 7 lines 66-68), thereby suggesting such a combination.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Koyama et al. (US 5384501 A) and Zanchi et al. (US 20150206600 A1) in further view of Cyr et al. (US 20060030277 A1), hereafter referred to as “Koyama”, “Zanchi”, and “Cyr”, respectively.
Regarding claims 3 and 4, Koyama and Zanchi teaches:
the first switch comprises a transistor (Koyama switches in Fig. 9 comprise switch transistors, per claim 3) wherein the transistor has a gate driven by the first control signal (transistor switches in Koyama Fig. 9 are controlled at the gate by control voltages Vc1, Vc2, Vcn, per claim 4).
However, Koyama and Zanchi is silent in teaching a NMOS transistor and a PMOS transistor connected back-to-back with the NMOS transistor, wherein the NMOS transistor has a gate driven by the first control signal, wherein the PMOS transistor has a gate driven by the second control signal inverted from the first control signal.
Cyr teaches:
two transistors connected back-to-back (Fig. 32, MOS transistors 358a, 358b are connected to form a switch, per paragraph [0086]), wherein a first transistor has a gate driven by a first control signal, wherein a second transistor has a gate driven by a second control signal inverted from the first control signal (per paragraph [0086] lines 9-15, digital signal B0 and it’s logical inverse
B
0
¯
control voltage to exceed threshold voltage of the MOS transistor, shown at the gates of 358a and 358b).
It would have been obvious to replace the switches in Koyama and Zanchi (Zanchi, Figs. 2 and 3) with the MOS switches, as taught by Cyr (Fig. 32), to tune the reactance of the varactor diode (per paragraph [0086] lines 17-20), thereby suggesting the obviousness of such a combination. As a resultant of Koyama, Zanchi, and Cyrit would further be obvious to implement an NMOS and PMOS transistors as they are common MOS transistors in the art (e.g. p-type and n-type MOS transistors suggested for elements 194a-194d in Fig. 13, in paragraph [0104] lines 1-4), thereby suggesting the obviousness of such a combination.
Allowable Subject Matter
Claims 10, 11, 12, 14-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 10, 11, 12, 14, and 15:
the cited prior art of record, either singly or in proper combination, Koyama et al. (US 5384501 A), does not teach or make obvious, along with the other claimed features, “the varactor diode has a voltage droop that is compensated by the unity gain buffer” per claim 10,
“the varactor driver has power consumption equal to or less than 50 pW”, per claim 11,
“the varactor driver has a fast response with an RC time constant equal to or less than 10 ps” per claim 12,
“the varactor driver comprises two or more varactor drivers” per claim 14, and
“a signal source coupled to the varactor driver through the first switch to provide an input voltage to the varactor driver” per claim 15.
Claim 16-21 are objected to as being dependent on objected claim 15.
Conclusion
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/Malane Lieng/ Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/ Supervisory Patent Examiner, Art Unit 2843
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