DETAILED ACTION
This office action is in response to amendments filed on 8/26/2026.
Claims 1, 3, 4, 6, 7, 9, 10, 13-16, 19 and 20 are amended.
Claims 1 – 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 7 and 13 – 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Le Grand et al (USPAT 8892403, prior art part of IDS dated 1/10/2025, hereinafter Le Grand), in view of Camacho et al (US 20140379169, hereinafter Camacho).
As per claim 1, Le Grand discloses: An apparatus, comprising:
a plurality of sensors; (Le Grand figure 1: sensors 106.)
a plurality of aggregator circuits coupled to corresponding subsets of the plurality of sensors; (Le Grand figure 1: sensor processor(s) 104.)
a plurality of client circuits including a particular client circuit configured to: generate a request corresponding to a particular sensor of the plurality of sensors; (Le Grand figure 1 and col 3, lines 9 – 12: “The acquired sensor data may then optionally be provided to one or more location-determination algorithms that facilitate determining the location associated with the mobile device.”)
an aggregation processor circuit configured to: and relay the request to a particular aggregator circuit of the plurality of aggregator circuits; and wherein the particular aggregator circuit is configured to relay the request to the particular sensor included in a particular subset of the plurality of sensors coupled to the aggregator circuit. (Le Grand figure 1: main application processor 102; col 7, lines 1 – 3: “the main application processor 102 may receive data indicating a request for GPS and Wi-Fi sensor data for the past thirty seconds.”; figure 2; col 8, line 65 – col 9, line 1: “receiving by a sensor processor and from the main application processor, data indicating a request to collect sensor data using one or more sensors of the mobile device.”; col 10, lines 48 – 50: “At block 204, the method 200 includes in response to receiving the data indicating the request, the sensor processor determining sensor data using the one or more sensors.”)
Le Grand did not explicitly disclose:
and store the request in a shared memory circuit included in the client circuit;
retrieve the request from the shared memory circuit included in a particular client circuit;
However, Camacho teaches:
and store the request in a shared memory circuit included in the client circuit; retrieve the request from the shared memory circuit included in a particular client circuit; (Camacho [0047]: “a shared vehicle server 170 comprises an interface for receiving requests to schedule a use of an identified vehicle (e.g. vehicle 102) by an identified vehicle user for which downloading previously stored vehicle user information from the vehicle user database 109 is desired. Turning briefly to FIG. 4, the shared vehicle server 170, based upon interactions with requesting users (e.g. via a Web page interface to vehicle user browser applications), generates a scheduled use record.”; [0048]: “the shared vehicle server 170 is configured to maintain a time-sorted listing of pending personalized information downloads, corresponding to the scheduled use records.”; [0049]: “the shared vehicle server 170 can operate as one of many such servers that schedule and initiate download requests to the vehicle user information server 145. Alternatively, the shared vehicle server 170 operates as an aggregator of requests from other servers that receive and forward requests for particular users (e.g. car rental agencies) in a hierarchical request handling scheme. In that case, the shared vehicle server 170 (and other similar servers for multiple car rental/share agencies) are responsible for providing the download request at any time prior to the actual download time. The vehicle user information server 145 handles the actual scheduling of downloads corresponding to the requests.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Camacho into that of Le Grand in order to store the request in a shared memory circuit included in the client circuit; retrieve the request from the shared memory circuit included in a particular client circuit. One of ordinary skill in the art can easily see that having the client device save the requests locally to be retrieved by a server later is a commonly known and used alternative design to the ones raised in Le Grand, as it is just a design choice to have specific device store the requests, and is therefore rejected under 35 USC 103.
As per claim 6, the combination of Le Grand and Camacho further teach:
The apparatus of claim 1, wherein the plurality of client circuits and the aggregation processor circuit are located on a first integrated circuit, and wherein the plurality of aggregator circuits are located on corresponding ones of a plurality of second integrated circuits. (Le Grande col 3, lines 28 – 41.)
As per claim 7, it is the method variant of claim 1 and is therefore rejected under the same rationale.
As per claim 13, it is the method variant of claim 6 and is therefore rejected under the same rationale.
As per claim 14, it is the system variant of claim 1 and is therefore rejected under the same rationale.
As per claim 15, the combination of Le Grand and Camacho further teach:
The system of claim 14, wherein the system-on-a-chip includes an aggregation processor configured to: receive the data from the corresponding aggregator circuit; write the data into a memory circuit shared by the particular client circuit and the aggregation processor; and send a message to the particular client indicating that the data has been written to the memory circuit. (Le Grande col 11, lines 12 – 34.)
As per claim 16, the combination of Le Grand and Camacho further teach:
The system of claim 15, wherein the particular client is configured, in response to receiving the message from the aggregation processor, to retrieve the data from the memory circuit. (Le Grande col 11, lines 12 – 34.)
Claim(s) 2, 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Le Grande and Camacho, and further in view of Srivastava (USPAT 9600251).
As per claim 2, the combination of Le Grand and Camacho did not explicitly teach:
The apparatus of claim 1, wherein the request has an associated quality-of-service level, and wherein to relay the request to the particular aggregator circuit, the aggregation processor circuit is further configured to: perform a comparison of the associated quality-of-service level of the request with corresponding quality-of-service levels associated with a plurality of previously received requests; establish an order for relaying the request and the plurality of previously received requests using a result of the comparison; and relay the request and the plurality of previously received requests using the order.
However, Srivastava teaches:
The apparatus of claim 1, wherein the request has an associated quality-of-service level, and wherein to relay the request to the particular aggregator circuit, the aggregation processor circuit is further configured to: perform a comparison of the associated quality-of-service level of the request with corresponding quality-of-service levels associated with a plurality of previously received requests; establish an order for relaying the request and the plurality of previously received requests using a result of the comparison; and relay the request and the plurality of previously received requests using the order. (Srivastava figure 10.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Srivastava into that of Le Grand and Camacho in order to have the request has an associated quality-of-service level, and wherein to relay the request to the particular aggregator circuit, the aggregation processor circuit is further configured to: perform a comparison of the associated quality-of-service level of the request with corresponding quality-of-service levels associated with a plurality of previously received requests; establish an order for relaying the request and the plurality of previously received requests using a result of the comparison; and relay the request and the plurality of previously received requests using the order. Srivastava figure 10 and accompanying description teaches such rearrange of request would aid in the execution efficiency of the overall system, and thus the combination of references would enhance the overall appeals of all references and is therefore rejected under 35 USC 103.
As per claim 8, the combination of Le Grand and Camacho did not explicitly teach:
The method of claim 7, wherein relaying, by the aggregation processor, the request to the particular aggregator circuit includes determining an order for relaying the request along with a plurality of previously received requests according to respective quality-of-service levels.
However, Srivastava teaches:
The method of claim 7, wherein relaying, by the aggregation processor, the request to the particular aggregator circuit includes determining an order for relaying the request along with a plurality of previously received requests according to respective quality-of-service levels. (Srivastava figure 10.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Srivastava into that of Le Grand and Camacho in order to have the request has an associated quality-of-service level, and wherein to relay the request to the particular aggregator circuit, the aggregation processor circuit is further configured to: perform a comparison of the associated quality-of-service level of the request with corresponding quality-of-service levels associated with a plurality of previously received requests; establish an order for relaying the request and the plurality of previously received requests using a result of the comparison; and relay the request and the plurality of previously received requests using the order. Srivastava figure 10 and accompanying description teaches such rearrange of request would aid in the execution efficiency of the overall system, and thus the combination of references would enhance the overall appeals of all references and is therefore rejected under 35 USC 103.
As per claim 9, the combination of Le Grand, Camacho and Srivastava further teaches:
The method of claim 8, further comprising initializing respective quality-of-service levels for the plurality of clients as part of a boot operation of a computer system that includes the plurality of clients, the aggregation processor, the plurality of aggregator circuits, and the plurality of sensors. (Srivastava figure 10.)
Claim(s) 3, 4, 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Le Grande and Camacho, and further in view of Pandey et al (USPAT 20230214292, hereinafter Pandey).
As per claim 3, the combination of Le Grand and Camacho did not explicitly teach:
The apparatus of claim 1, wherein to generate the request, the particular client is further configured to write a message to a particular mailbox register of a plurality of mailbox registers included in the aggregation processor circuit.
However, Pandey teaches:
The apparatus of claim 1, wherein to generate the request, the particular client is further configured to write a message to a particular mailbox register of a plurality of mailbox registers included in the aggregation processor circuit. (Pandey [0008])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Pandey into that of Le Grand and Camacho in order to generate the request, the particular client is further configured to write a message to a particular mailbox register of a plurality of mailbox registers included in the aggregation processor circuit. Pandey has shown that the claimed limitation is merely a commonly known steps in data forwarding in distributed execution system, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results of forwarding request to appropriate sensor via register and is therefore rejected under 35 USC 103.
As per claim 4, the combination of Le Grand, Camacho and Pandey further teaches:
The apparatus of claim 3, wherein the message includes an address corresponding to a location in a memory circuit shared between the particular client and the aggregation processor circuit, and wherein to receive the request from the particular client circuit, the aggregation processor circuit is further configured to retrieve data indicative of the request from the memory circuit using the address. (Pandey [0008] and [0020])
As per claim 10, it is the method variant of claim 3 and is therefore rejected under the same rationale.
As per claim 11, it is the method variant of claim 4 and is therefore rejected under the same rationale.
Claim(s) 5 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Le Grande and Camacho, and further in view of Seago et al (USPAT 20120005341, hereinafter Seago).
As per claim 5, the combination of Le Grand and Camacho did not explicitly teach:
The apparatus of claim 1, wherein to generate the request, the particular client is further configured to write a message to a particular mailbox register of a plurality of mailbox registers included in the aggregation processor circuit.
However, Seago teaches:
The apparatus of claim 1, wherein the aggregation processor circuit is further configured to relay the request to the particular aggregator circuit using a first communication protocol, and wherein the particular aggregator circuit is further configured to relay the request to the particular sensor using a second communication protocol different than the first communication protocol. (Seago [0026])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Seago into that of Le Grand and Camacho in order to have the aggregation processor circuit is further configured to relay the request to the particular aggregator circuit using a first communication protocol, and wherein the particular aggregator circuit is further configured to relay the request to the particular sensor using a second communication protocol different than the first communication protocol. Seago has shown that the claimed limitation is merely a commonly known steps in data forwarding in distributed execution system, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results of forwarding request to appropriate sensor via register and is therefore rejected under 35 USC 103.
As per claim 12, it is the method variant of claim 5 and is therefore rejected under the same rationale.
Claim(s) 17 – 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Le Grande and Camacho, and further in view of Rodriguez Bravo et al (US 20190155659, hereinafter Rodriguez Bravo).
As per claim 17, the combination of Le Grand and Camacho did not explicitly teach:
The system of claim 15, wherein the system-on-a-chip is further configured to initialize one or more quality-of-service levels for the aggregation processor during a boot process.
However, Rodriguez Bravo teaches:
The system of claim 15, wherein the system-on-a-chip is further configured to initialize one or more quality-of-service levels for the aggregation processor during a boot process. (Rodrigues Bravo [0003])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Rodriguez Bravo into that of Le Grand and Camacho in order to the system-on-a-chip is further configured to initialize one or more quality-of-service levels for the aggregation processor during a boot process. Rodrigues Bravo [0003] teaches the claimed steps are merely commonly known and used steps to ensure sensor health and thus applicants have merely claimed the combination of known parts in the field to achieve predictable results of monitor distributed resource health for load balancing purpose and is therefore rejected under 35 USC 103.
As per claim 18, the combination of Le Grand, Camacho and Rodriguez Bravo further teach:
The system of claim 17, wherein to initialize the one or more quality-of-service levels for the aggregation processor, the system-on-a-chip is further configured to assign corresponding quality-of-service levels for the plurality of sensors. (Rodrigues Bravo [0003])
As per claim 19, the combination of Le Grand, Camacho and Rodriguez Bravo further teach:
The system of claim 18, wherein to initialize the one or more quality-of-service levels for the aggregation processor, the system-on-a-chip is further configured to assign corresponding quality-of-service levels for the plurality of client circuits. (Rodrigues Bravo [0003])
As per claim 20, the combination of Le Grand, Camacho and Rodriguez Bravo further teach:
The system of claim 18, wherein a different sensor of the plurality of sensors is configured, in response to detecting an interrupt condition, to send an interrupt to a different aggregator circuit coupled to the different sensor, wherein the different aggregator circuit is configured to relay the interrupt to the aggregation processor, and wherein the aggregation processor is further configured to relay the interrupt to a different client circuit of the plurality of client circuits that corresponds to the different sensor. (Rodrigues Bravo [0003])
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 – 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M SWIFT whose telephone number is (571)270-7756. The examiner can normally be reached Monday - Friday: 9:30 AM - 7PM.
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/CHARLES M SWIFT/Primary Examiner, Art Unit 2196
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