DETAILED ACTION
Notice to Applicant
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the Response dated 02/05/2026, claims 1-4 and 13-16 have been elected and claims 5-12 and 17-24 have been withdrawn.
Priority
3. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
4. The specification is objected to due to the following informality.
In paragraph 33, it appears that reference to Figure 2B in line 1 should be corrected so that reference is made to Figure 3B.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1 and 13 are rejected under 35 U.S.C. 103 as being obvious in view of Sobolewski et al. (US 2022/0291278 – hereinafter “Sobolewski”) and Tamamura et al. (US 4,833,403 – hereinafter “Tamamura”).
Per claim 1, Sobolewski teaches a test and measurement system, comprising:
a device under test (DUT) interface (Fig. 3; DUT interface 58; ¶19) structured to couple to at least one DUT (A DUT interface 58 is structured to couple to a DUT (Figs. 3-4; ¶19 and 21)); and
a measurement instrument (Fig. 3; measurement device 40; ¶17) coupled to the interface and including one or more processors (Fig. 3; processors 46; ¶17) configured to execute code that causes the one or more processors, to perform a double-pulse test on the DUT (The measurement device 40 includes one or more processors 46 and is coupled to a power device 50 that includes the DUT interface 58. A double pulse test may be performed on the DUT (Fig. 3; ¶17-19, 21, and 49)),
However, Sobolewski does not explicitly teach the system wherein the one or more processors are configured to, when performing a double-pulse test on the DUT, characterize settling error during a first pulse of the double-pulse test; and compensate the settling error characterized during the first pulse of the double-pulse test from measurements made during a second or subsequent pulse of the double-pulse test.
In contrast, Tamamura teaches a method for measuring settling characteristics of a device under test (DUT) wherein measurement data from the DUT is recorded and compared to reference data. Compensation of the measurement data is performed by removing an error component from the measurement data based on the comparison (Figs. 1 and 6; col. 1, line 66 – col. 2, line 22 and col. 3, lines 63-66).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Sobolewski such that the one or more processors are configured to, when performing a double-pulse test on the DUT, characterize settling error during a first pulse of the double-pulse test; and compensate the settling error characterized during the first pulse of the double-pulse test from measurements made during a second or subsequent pulse of the double-pulse test. One of ordinary skill would make such a modification for the purpose of removing an error component in measurement data due to a settling characteristic of a measurement system (Sobolewski; col. 1, line 66 – col. 2, line 22).
Per claim 13, Sobolewski teaches a method in a test and measurement system, comprising:
providing a device under test (DUT) interface (Fig. 3; DUT interface 58; ¶19) structured to couple to at least one DUT (A DUT interface 58 is structured to couple to a DUT (Figs. 3-4; ¶19 and 21)); and,
a measurement instrument (Fig. 3; measurement device 40; ¶17) coupled to the interface (The measurement device 40 includes one or more processors 46 and is coupled to a power device 50 that includes the DUT interface 58. A double pulse test may be performed on the DUT (Fig. 3; ¶17-19, 21, and 49)).
However, Sobolewski does not explicitly teach the method comprising characterizing settling error during a first pulse of a double-pulse test performed on the DUT; and compensating the settling error characterized during the first pulse of the double-pulse test from measurements made during a second or subsequent pulse of the double-pulse test.
In contrast, Tamamura teaches a method for measuring settling characteristics of a device under test (DUT) wherein measurement data from the DUT is recorded and compared to reference data. Compensation of the measurement data is performed by removing an error component from the measurement data based on the comparison (Figs. 1 and 6; col. 1, line 66 – col. 2, line 22 and col. 3, lines 63-66).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Sobolewski such that it comprises characterizing settling error during a first pulse of a double-pulse test performed on the DUT; and compensating the settling error characterized during the first pulse of the double-pulse test from measurements made during a second or subsequent pulse of the double-pulse test. One of ordinary skill would make such a modification for the purpose of removing an error component in measurement data due to a settling characteristic of a measurement system (Sobolewski; col. 1, line 66 – col. 2, line 22).
7. Claims 4 and 16 are rejected under 35 U.S.C. 103 as being obvious in view of Sobolewski and Tamamura, in further view Nozaki (US 2008/0309355 – hereinafter “Nozaki”).
Per claim 4, Sobolewski in view of Tamamura does not explicitly teach the test and measurement system according to claim 1, in which the first and second pulses of the double-pulse test are separated by a time period determined by a settling time period.
In contrast, Nozaki teaches a semiconductor evaluation device for measuring a dynamic on-resistance of a switching element 1 including a pulse generating circuit 2 configured to applies a series of pulses to the gate of the switching element 1. The pulses, which turn the switching device on and off, are separated by a time period that avoids waveform distortion (Figs. 1, 2A, and 2B; ¶38, 45-46 and 51).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Sobolewski such that the first and second pulses of the double-pulse test are separated by a time period determined by a settling time period. One of ordinary skill would make such a modification for the purpose of avoiding waveform distortion (Nozaki; Figs. 2A and 2B).
Per claim 16, Sobolewski in view of Tamamura does not explicitly teach the method according to claim 13, further comprising initiating the second pulse of the double-pulse test a time period after the first pulse of the double-pulse test that is determined by a settling time period.
In contrast, Nozaki teaches a semiconductor evaluation device for measuring a dynamic on-resistance of a switching element 1 including a pulse generating circuit 2 configured to applies a series of pulses to the gate of the switching element 1. The pulses, which turn the switching device on and off, are separated by a time period that avoids waveform distortion (Figs. 1, 2A, and 2B; ¶38, 45-46 and 51).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Sobolewski such that the first and second pulses of the double-pulse test are separated by a time period determined by a settling time period. One of ordinary skill would make such a modification for the purpose of avoiding waveform distortion (Nozaki; Figs. 2A and 2B).
Claim Objections
8. Claims 2-3 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Per claim 2, the prior art of record is silent on the test and measurement system according to claim 1, wherein the code that causes the one or more processors to compensate the settling error further comprises code that causes the one or more processors to determine a change in a voltage measured during the first pulse and during the second or subsequent pulse, and to determine a change in a current measured during the first pulse and during the second or subsequent pulse. Claim 3 is consequently objected to due to its dependence on claim 2.
Per claim 14, the prior art of record is silent on the method according to claim 13, wherein compensating the settling error comprises determining a change in a voltage measured during the first pulse and during the second or subsequent pulse, and to determine a change in a current measured during the first pulse and during the second or subsequent pulse. Claim 15 is consequently objected to due to its dependence on claim 14.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAS A. SANGHERA whose telephone number is (571)272-4787. The examiner can normally be reached M-Th, alt. Fri, 8-5 EST.
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/JAS A SANGHERA/Primary Examiner, Art Unit 2852