Prosecution Insights
Last updated: April 19, 2026
Application No. 18/641,518

POWER LINE CARRIER COMMUNICATION APPARATUS, METHOD, AND SYSTEM

Final Rejection §103
Filed
Apr 22, 2024
Examiner
FOTAKIS, ARISTOCRATIS
Art Unit
2633
Tech Center
2600 — Communications
Assignee
Hoymiles Power Electronics Inc.
OA Round
2 (Final)
71%
Grant Probability
Favorable
3-4
OA Rounds
2y 11m
To Grant
99%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allow Rate
531 granted / 745 resolved
+9.3% vs TC avg
Strong +31% interview lift
Without
With
+30.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
35 currently pending
Career history
780
Total Applications
across all art units

Statute-Specific Performance

§101
4.3%
-35.7% vs TC avg
§103
53.6%
+13.6% vs TC avg
§102
19.3%
-20.7% vs TC avg
§112
16.5%
-23.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 745 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed February 12, 2026 have been fully considered but they are not persuasive. Applicants submit that the discrete voltage levels (V1-V8) of Gazit are output by the SIMLO converter 10, two discrete values of voltage on each output (O/Pn, n=1-7) may alternate from one to each other by virtue of multiple pulse width modulation (PWM) signals from PWM unit 14, the duty cycle and the phase difference belong to the PWM signals, not the discrete voltage levels, the duty cycle and the phase difference of the PWM signals are configured to alternate two discrete values of voltage. However, in the amended claim 1, the communication processing unit is configured for modulating a communication signal into a plurality of control signals with a preset duty cycle and a preset phase difference. Thus, the plurality of control signals in the amended claim 1 are different from the discrete voltage levels (V1-V8) of Gazit. Examiner submits that Gazit teaches of modulating a communication signal into a plurality of control signals (V1-V8 as shown in Fig.2B) with a preset duty cycle (preset duty cycle according to PWM control signal 20, Fig.2B) and a preset phase difference (preset phase difference between each pair of voltages, for example V1 and V2, Fig.2B). The duty cycle and the phase difference are set and controlled by PWM control signals (#20, Fig.2B). Thus, Gazit teaches of modulating a communication signal into a plurality of control signals (V1-V8 as shown in Fig.2B) controlled by PWM controller (#14, Fig.2C) to have a preset duty cycle and a preset phase difference (as shown in Fig.2B). Therefore, the plurality of control signals in the amended claim 1 are the same as the discrete voltage levels (V1-V8) of Gazit. Applicants submit that the purpose and the technical means of the amended claim 1 are different from those of Freear. Freear does not disclose the feature "the switching network is configured for generating a multi-level carrier signal corresponding to the communication signal according to the plurality of control signals, wherein (n+1)th and lower orders of harmonics contained in the carrier signal are less than or equal to a first threshold, respectively, n represents the number of levels of the carrier signal, and n is an odd number greater than or equal to 3" of the amended claim 1. Examiner submits that Gazit teaches of providing the function of harmonic cancellation in converter 107 (Paragraph 0055). Freear teaches of generating a multi-level carrier signal (Figures 24 and 44), wherein (n+1)th and lower orders of harmonics contained in the carrier signal are less than or equal to a first threshold (harmonic component of the signal is maintained below a first threshold, Abstract, Paragraph 0019 and Fig.23), respectively, n represents the number of levels of the carrier signal (n= 3 or 5, Figures 23 – 24), and n is an odd number greater than or equal to 3 (n = 3 or 5, Figures 23 – 24) (Paragraphs 0009 and 0029). Therefore, Freear teaches of having the (n+1)th and lower orders of harmonics contained in the carrier signal to be less than or equal to a first threshold for improved power quality and efficiency. Thus, the combination of Gazit and Freear teach all the limitations of claim 1. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1 – 2, 4, 14 – 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Gazit et al (US 2020/0136523) in view of Freear et al (US 2015/0348531). Re claims 1 and 14, Gazit teaches of a power line carrier communication apparatus (#107, Figures 1H and 2C), comprising a communication processing unit (#10 and #14, Figures 1H and 2C), a switching network (#12a, Figures 1B and 1D, #12d, Fig.1J, #12, Figures 1H and 2C), and an impedance network (#16a, Figures 1B and 1D, #16d, Fig.1J, #16, Figures 1H and 2C); wherein the communication processing unit is configured for modulating a communication signal into a plurality of control signals (V1-V8 as shown in Fig.2B) with a preset duty cycle (preset duty cycle according to PWM control signal 20, Fig.2B) and a preset phase difference (preset phase difference between each pair of voltages, for example V1 and V2, Fig.2B), and the communication signal comprises communication data (PWM, Paragraph 0049 and #14, Figures 1H and 2C); the switching network is configured for generating a multi-level carrier signal (output of #12, O/P1 – O/P7, Figures 1H and 2B – 2C, multi-level carrier signal as shown in Fig.2B) corresponding to the communication signal according to the plurality of control signals (see Table 1 and Fig.2B), wherein n represents the number of levels of the carrier signal (n=7, Table 1 and Fig.2B), and n is an odd number greater than or equal to 3 (n=7, Table 1 and Fig.2B); and the impedance network is configured for filtering the carrier signal (L2 of Figures 1B, 1D and 1J, Paragraph 0056) and then coupling a filtered carrier signal to a power line (Line and Neutral line, Figures 1D, 1G, 1H and 2C). Gazit further teaches of providing the function of harmonic cancellation in converter 107 (Paragraph 0055). However, Gazit does not specifically mention of the (n+1)th and lower orders of harmonics contained in the carrier signal are less than or equal to a first threshold, respectively. Freear teaches of generating a multi-level carrier signal (Figures 24 and 44), wherein (n+1)th and lower orders of harmonics contained in the carrier signal are less than or equal to a first threshold (harmonic component of the signal is maintained below a first threshold, Abstract, Paragraph 0019 and Fig.23), respectively, n represents the number of levels of the carrier signal (n= 3 or 5, Figures 23 – 24), and n is an odd number greater than or equal to 3 (n = 3 or 5, Figures 23 – 24) (Paragraphs 0009 and 0029). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have performed the harmonic cancellation in Gazit by having the (n+1)th and lower orders of harmonics contained in the carrier signal to be less than or equal to a first threshold for improved power quality and efficiency. Re claim 15, Gazit teaches of a power line carrier communication system (PLC, Paragraph 0045 and #100, Fig.1A), comprising a power line carrier communication apparatus (#107, Figures, 1A, 1H and 2C), wherein power line carrier communication apparatus comprises a communication processing unit, a switching network, and an impedance network; the communication processing unit is configured for modulating a communication signal into plurality of control signals (V1-V8 as shown in Fig.2B) with a preset duty cycle (preset duty cycle according to PWM control signal 20, Fig.2B) and a preset phase difference (preset phase difference between each pair of voltages, for example V1 and V2, Fig.2B), wherein the communication signal comprises communication data; the switching network is configured for generating a multi-level carrier signal corresponding to the communication signal according to the plurality of control signals, wherein n represents the number of levels of the carrier signal, and n is an odd number greater than or equal to 3; and the impedance network is configured for filtering the carrier signal and then coupling a filtered carrier signal to a power line (see claim 1). Gazit further teaches of providing the function of harmonic cancellation in converter 107 (Paragraph 0055). However, Gazit does not specifically mention of the (n+1)th and lower orders of harmonics contained in the carrier signal are less than or equal to a first threshold, respectively. Freear teaches of generating a multi-level carrier signal (Figures 24 and 44), wherein (n+1)th and lower orders of harmonics contained in the carrier signal are less than or equal to a first threshold (harmonic component of the signal is maintained below a first threshold, Abstract, Paragraph 0019 and Fig.23), respectively, n represents the number of levels of the carrier signal (n= 3 or 5, Figures 23 – 24), and n is an odd number greater than or equal to 3 (n = 3 or 5, Figures 23 – 24) (Paragraphs 0009 and 0029). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have performed the harmonic cancellation in Gazit by having the (n+1)th and lower orders of harmonics contained in the carrier signal to be less than or equal to a first threshold for improved power quality and efficiency. Re claims 2 and 16, Gazit teaches of wherein the switching network comprises a plurality of switching elements (two series switches of switch network Sn, Fig.1D and Fig.1F, Paragraphs 0032 and 0034), and the communication processing unit is further configured for providing the plurality of control signals to the corresponding plurality of switching elements, respectively (as shown in (#12a, Figures 1B and 1D, #12d, Fig.1J). Re claims 4 and 18, Gazit teaches of wherein the communication processing unit (#10 and #14, Figures 1H and 2C) further comprises a protocol processor (#14, PWM, Figures 1H and 2C) and a modulation module; wherein the protocol processor (#14, PWM, Figures 1H and 2C) is configured for encapsulating the communication data in accordance with a preset communication protocol to obtain the communication signal (PWM (Pulse Width Modulation) protocol, Paragraphs 0024 and 0042); and the modulation module (#10, Fig.2B) is configured for modulating the communication signal into control signals with a preset duty cycle (preset duty cycle according to PWM control signal 20, Fig.2B) and a preset phase difference (preset phase difference between each pair of voltages, for example V1 and V2, Fig.2B). Claims 3 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Gazit and Freear in view of Hwang et al (US 2014/0194076). Re claims 3 and 17, Gazit and Freear teach all the limitations of claims 1 and 15 as well as Freear teaches of the (n+1)th and lower orders of harmonics being in a Fourier expansion equation of the carrier signal (Paragraph 0131 and Fig.18). Gazit furthers shows that a duty cycle will determine the phase difference in the waveform as set by each voltage pair (Fig.2B). However, Gazit and Freear do not specifically teach of guaranteeing coefficients of the (n+1)th and lower orders of harmonics of the carrier signal to be less than or equal to a second threshold, by modulating a duty cycle and a phase difference of control signals. Hwang teaches of guaranteeing coefficients of the harmonics of the carrier signal to be less than or equal to a second threshold, by modulating a duty cycle (Paragraphs 0008 and 0035, Equation 1). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have used a Fourier expansion so as to determine the (n+1)th and lower orders of harmonics. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have determined coefficients of the harmonics of the carrier signal to be less than or equal to a second threshold by modulating a duty cycle and a phase difference of control signals to rapidly minimize harmonic spurs. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Gazit and Freear in view of Achtzehn et al (US 2019/0097543). Re claim 13, Gazit and Freear teach all the limitations of claim 1 except of further comprising a drive unit configured for generating a drive signal of the switching network according to the plurality of control signals. Achtzehn teaches of a drive unit (#20, Fig.1) configured for generating a drive signal of the switching network according to the plurality of control signals (Driver 20 applies voltage signals to the gate of the transistor of converter switch 18 to drive the converter switch, Paragraph 0026). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have generated a drive signal of the to drive the switching network according to the plurality of control signals to improves a switch's performance by ensuring rapid on/off switching. Allowable Subject Matter Claims 5 – 12 and 19 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARISTOCRATIS FOTAKIS whose telephone number is (571)270-1206. The examiner can normally be reached M-F 8:30am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sam K Ahn can be reached at (571) 272-3044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ARISTOCRATIS FOTAKIS/ Primary Examiner, Art Unit 2633
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Prosecution Timeline

Apr 22, 2024
Application Filed
Nov 24, 2025
Non-Final Rejection — §103
Feb 12, 2026
Response Filed
Mar 06, 2026
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
71%
Grant Probability
99%
With Interview (+30.8%)
2y 11m
Median Time to Grant
Moderate
PTA Risk
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