DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Saad et. al., (A 1.8–3.8-GHz Power Amplifier With 40% Efficiency at 8-dB Power Back-Off, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 66, NO. 11, NOVEMBER 2018, cited by the applicant) in view of Chen (US 2022/0255506 A1).
Regarding Claim 1 Saad teaches the distributed efficient power amplifier (DEPA) architecture comprising a main amplifier, and multiple auxiliary amplifiers distributed along an output power combiner (Fig. 2 and Fig. 5, Section II-B: Proposed Architecture).
the 3-dB input power splitter that divides the input signal (
R
F
in
) between the main amplifier and the auxiliary path (Fig. 2 and Fig. 5, Section II-B: Proposed Architecture);
the main amplifier connected to one output of the initial power splitter ((Fig. 2 and Fig. 5, Section II-B: Proposed Architecture);
PNG
media_image1.png
270
577
media_image1.png
Greyscale
Fig. 1 of Saad Topology of the (distributed efficient power amplifier) DEPA.
the even power splitter network (including 3-way and 2-way Wilkinson dividers) configured to divide the auxiliary input path into
N
equal signals for the
N
auxiliary amplifiers. (Note: For a system with
N
total auxiliaries,
N
-
1
secondary division stages or paths split the signal, Fig. 2 and Fig. 5, Section II-B: Proposed Architecture);
the multiple auxiliary amplifiers (
Aux
1
through
Aux
N
) distributed along the output combiner (Fig. 2 and Fig. 5, Section II-B: Proposed Architecture);
the output power combiner consisting of
N
quarter-wave transmission line sections with varying characteristic impedances (
Z
0
through
Z
N
-
1
) connected in series (Fig. 2 and Fig. 5, Section II-B: Proposed Architecture);
where the main amplifier is connected to the input side (
Z
0
) of the multi-section output power combiner (Fig. 2 and Fig. 5, Section II-B: Proposed Architecture);
where the auxiliary amplifiers are connected at the nodes between the transmission line sections of the output combiner (Fig. 2 and Fig. 5, Section II-B: Proposed Architecture);
where the main amplifier operates alone up to the transition point (low-power region), and the auxiliary amplifiers turn on simultaneously at the transition point when the input/output power reaches the predetermined back-off threshold (Fig. 3, Fig. 4, and Fig. 6(a)-(b), Section II-C: DEPA Design Equations). Saad, however, doesn’t teach that the (N-1) auxiliary amplifiers include an auxiliary amplifier having maximum output power larger than maximum output power of the main amplifier.
In Saad's theoretical formulation and design examples, individual auxiliary amplifiers are sized based on admittance discontinuities (yielding maximum currents/powers such as
I
A
i
,
max
); however, the main amplifier is designed to deliver peak back-off efficiency while the auxiliaries combine incrementally, and individual auxiliaries do not possess a maximum output power larger than the main amplifier's peak foundational capacity in the symmetrical/graded progression described (furthermore, practical implementations explicitly utilize equal-sized devices for all main and auxiliary units as noted in Section III-A).
While Saad describes general load modulation and balanced configurations, standard primary implementations often focus on symmetrical structures or do not explicitly mandate that an auxiliary/peaking amplifier has a maximum output power strictly larger than the maximum output power of the main amplifier (
P
peak
>
P
main
) optimized across multi-level back-offs for arbitrary efficiency peaks.
However, specifically an asymmetric configuration where the peaking/auxiliary amplifier possesses a larger maximum output power compared to the main amplifier to achieve higher efficiency peaks at deeper back-off levels—is explicitly taught by many prior arts in the similar field of multi-way Doherty Amplifiers. As for example,
Liu (US 2014/0320214) teaches asymmetric load-modulated balanced amplifier configurations utilizing scaled device sizes and asymmetric power capabilities to optimize back-off efficiency peaks (see Liu reference structures, corresponding device sizing scaling factor
α
>
1
, FIG. 7, paragraph [0087]).
Kim (US 2012/0176194) teaches asymmetric Doherty and load-modulation architectures where peaking amplifier power capacity exceeds the main amplifier capacity to widen the high-efficiency power back-off range (see Kim amplifier design principles, power scaling relationships, and efficiency versus output power performance characteristics).
Chen explicitly teaches reconfigurable asymmetrical load-modulated balanced amplifiers (ALMBA) wherein the peaking amplifier circuit comprises asymmetric power amplifiers with asymmetric current/power scaling characteristics (see e.g., Abstract; Summary, paragraphs [0005]–[0008]; FIGS. 1–2). Specifically, FIG. 2 (Col. 5, Lines 80–95) and paragraph [0096] illustrate an asymmetric arrangement where peaking amplifier BA2 (120a) has a physically larger size and higher power capacity than BA1 (118a) to manage larger back-off levels.
In such context, a Person of Ordinary Skill In The Art (POSITA) reviewing Saad would find it obvious to exemplify an asymmetric design variant by sizing parameters of the auxiliary/peaking amplifiers—drawing upon the explicit teachings of Liu, Kim, and Chen—to scale up the physical size and maximum output power of the peaking amplifier relative to the main amplifier. This modification involves routine adjustment of the transistor periphery and saturation currents (as taught by Chen at paragraphs [0087] and [0096]) within the quadrature-coupled layout of Saad to realize an asymmetric load-modulated topology.
As documented in the secondary art (e.g., Chen at paragraph [0003] and [0004]), modern communication standards like 5G featuring complex modulations exhibit a high Peak-to-Average Power Ratio (PAPR) exceeding 10 dB.
Also modifying the primary amplifier architecture to incorporate a larger peaking amplifier enables extended output power back-off (OBO) ranges (such as 10-dB OBO or greater), thereby resolving the limited OBO constraint of traditional symmetric architectures and drastically improving average power-added efficiency (PAE) when amplifying high-PAPR signals without sacrificing operational bandwidth (as supported by Chen, Table I, FIG. 30).
Claim 2 recites, the distributed power amplifier according to claim 1, wherein the output end of the auxiliary amplifier having maximum output power larger than maximum output power of the main amplifier is connected to an end portion on the output side of any one of transmission lines in a second and subsequent stages.
Wherein Saad in view Chen teaches all limitations of claim 1, Chen further in view of the generalized reconfigurable asymmetrical load-modulated balanced amplifier (ALMBA) framework (e.g., asymmetric power amplifiers BA1 and BA2 with distinct sizing/power scaling such as
α
>
1
and
σ
≠
1
as detailed in paragraphs [0006]-[0007], [0087], [0091], [0132]-[0133]) teaches utilizing asymmetric power configurations where an auxiliary amplifier features a maximum output power larger than that of the main amplifier.
A person of ordinary skill in the art (POSITA) would readily recognize that connecting the output of such a higher-power auxiliary amplifier to an output-side end portion of a transmission line in the second or subsequent stages (analogous to the staged active device placement in wideband distributed or multi-stage topologies) represents a routine design choice to manipulate load-modulation trajectories and extend back-off efficiency. Therefore, modifying the distributed power amplifier to connect the higher-power auxiliary amplifier to a second or subsequent stage transmission line represents a routine design choice within the established framework of asymmetrical load-modulated architectures.
Claim 3 recites, the distributed power amplifier according to claim 1, wherein the output end of the auxiliary amplifier having maximum output power larger than maximum output power of the main amplifier is connected to an end portion on the output side of a (N-1)-th stage transmission line.
Wherein Saad in view Chen teaches all limitations of claim 1, Chen further teaches asymmetrical load-modulated balanced amplifiers where auxiliary amplifiers feature scaled power characteristics relative to the main carrier amplifier (e.g., paragraphs [0006]-[0007], [0087]).
A person of ordinary skill in the art (POSITA) would find it a routine design choice to connect the output end of the higher-power auxiliary amplifier to a specific stage node, such as the (N-1)-th stage transmission line output, to achieve optimal active load modulation and high-efficiency operation over an extended dynamic range as taught by the generalized ALMBA principles. Therefore, modifying the amplifier configuration to connect the auxiliary amplifier output to the (N-1)-th stage transmission line represents a routine design choice within the established framework of asymmetrical load-modulated amplifiers.
Claim 4 recites, the distributed power amplifier according to claim 1, wherein a bias voltage of the main amplifier is set in such a way that the main amplifier operates in Class A or Class AB, and a bias voltage of the (N-1) auxiliary amplifiers is set in such a way that the (N-1) auxiliary amplifiers operate in Class C.
Wherein Saad in view Chen teaches all limitations of claim 1, and Chen explicitly describes that the carrier amplifier (main amplifier) can be configured with a Class AB, Class A, or Class B bias (e.g., paragraphs [0016], [0087], [0100]), and the pair of auxiliary amplifiers (peaking amplifiers) are biased in Class C mode (e.g., paragraphs [0009], [0013], [0087], [0132]).
A person of ordinary skill in the art (POSITA) would readily recognize that combining a Class AB/A main amplifier with Class C auxiliary amplifiers constitutes standard Doherty-like and pseudo-Doherty biasing strategies used to shape active load modulation and maximize back-off efficiency. Therefore, implementing these specific bias voltage settings for the main and auxiliary amplifiers represents a routine design choice within the established framework of asymmetrical load-modulated balanced amplifiers.
Claim 5 recites, the distributed power amplifier according to claim 1, wherein each of the (N-1) stages of transmission lines have an electrical length of approximately 90 degrees.
Wherein Saad in view Chen teaches all limitations of claim 1, and Chen explicitly describes quadrature couplers and transmission lines configured with a 90° electrical length (e.g., paragraphs [0011], [0013], [0087], [0091], [0118]).
A person of ordinary skill in the art (POSITA) would readily recognize that employing transmission lines or quarter-wave sections with an electrical length of approximately 90 degrees is a fundamental requirement for quadrature-coupled and network-based load modulation architectures to properly transform impedances and align phase relationships. Therefore, setting the electrical length of the transmission lines to approximately 90 degrees represents a routine design choice within the established framework of asymmetrical load-modulated balanced amplifiers.
Claim 6 recites, the distributed power amplifier according to claim 1, wherein a characteristic impedance of the (N-1) stages of transmission lines is set in such a way that a combining circuit including the (N-1) stages of transmission lines forms a Chebyshev type broadband impedance conversion circuit.
Wherein Saad in view Chen teaches all limitations of claim 1, and Chen teaches wideband impedance transformation and matching networks utilizing transmission lines, couplers, and frequency-dependent phase offsets to achieve ultrawideband performance (e.g., paragraphs [0014], [0087], [0104]-[0107]).
A person of ordinary skill in the art (POSITA) would recognize that utilizing Chebyshev-type or broadband matching circuit configurations for transmission line stages is a well-known engineering technique to optimize bandwidth and impedance transformation ratios in microwave amplifier design. Therefore, configuring the characteristic impedances to form a Chebyshev type broadband impedance conversion circuit represents a routine design choice within the established framework of asymmetrical load-modulated balanced amplifiers.
Claim 7 recites, the distributed power amplifier according to claim 1, further comprising a filter circuit having an impedance conversion function, wherein an input end of the filter circuit is connected to an end portion on the output side of a (N-1)-th stage transmission line, and an input impedance of the filter circuit is conjugate-matched with an output impedance at an end portion on the output side of the (N-1)-th stage transmission line.
Wherein Saad in view Chen teaches all limitations of claim 1, and Chen teaches the integration of matching networks, filter circuits, and impedance conversion structures connected to output transmission lines to realize optimal load modulation and power transfer (e.g., paragraphs [0014], [0091], [0104]-[0107]).
A person of ordinary skill in the art (POSITA) would readily understand that applying filter circuits with impedance conversion functions and conjugate-matching the input impedance of such filters to the preceding transmission line output is a standard microwave design practice for maximizing power delivery and preventing reflections. Therefore, incorporating a conjugate-matched filter circuit with an impedance conversion function represents a routine design choice within the established framework of asymmetrical load-modulated balanced amplifiers.
Claim 8 recites, the distributed power amplifier according to claim 1, further comprising an antenna connected to an end portion on the output side of a (N-1)-th stage transmission line, wherein an input impedance of the antenna is conjugate-matched with an output impedance at an end portion on the output side of the (N-1)-th stage transmission line.
Wherein Saad in view Chen teaches all limitations of claim 1, and Chen describes power amplifier output ports coupled to load networks and system environments where output power is delivered to load impedances (e.g., paragraphs [0005], [0087]).
A person of ordinary skill in the art (POSITA) would recognize that connecting an antenna as the final load to the output side of a transmission line stage—and ensuring conjugate matching between the antenna input impedance and the amplifier output impedance—represents standard transmitter integration practice. Therefore, connecting a conjugate-matched antenna to the output side of the transmission line represents a routine design choice within the established framework of asymmetrical load-modulated balanced amplifiers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
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