Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 16 and 1 objected to because of the following informalities:
Claim 16: the phrase “is directly contact with” should be rewritten as either “is in direct contact with” or “is directly in contact with”.
Claim 19: the phrase "has a coplaner surface" is used when it should say "have a coplaner surface".
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sio et al. (US 20210118805 A1).
Regarding claim 1, FIG. 2 of Sio et al. teaches a semiconductor structure comprising:
a first metal level (M1; FIG. 2; paragraph 0028) in a back-end-of-line (BEOL) structure (M1; FIG. 2; paragraph 0028);
a second metal level (M1; FIG. 2; paragraph 0028) in a backside power distribution network (BSPDN) (270; FIG. 2; paragraph 0018); and
a through silicon via (TSV) (250; FIG. 2; paragraph 0018; 205; FIG. 2; paragraph 0018) extending from the second metal level to the first metal level, wherein the TSV has a first portion (250; FIG. 2; paragraph 0018) and a second portion (205; FIG. 2; paragraph 0018) and a discontinuous increase in width from the first portion to the second portion.
Regarding claim 7, FIG. 2 of Sio et al. teaches the semiconductor structure of claim 1, wherein the first portion of the TSV (250; FIG. 2; paragraph 0018) has a first width, and the second portion of the TSV (205; FIG. 2; paragraph 0018) has a second width, and the second width is at least 5% more than the first width.
Regarding claim 15, FIG. 2 of Sio et al. teaches a semiconductor structure comprising:
a landing pad (M1; FIG. 2; paragraph 0028) in a back-end-of-line (BEOL) structure (M1; FIG. 2; paragraph 0028);
a backside power distribution network (BSPDN) (270; FIG. 2; paragraph 0018) in a backside dielectric layer (272; FIG. 2; paragraph 0018);
and a through silicon via (TSV) (205, 250; FIG. 2; paragraph 0018) extending from the backside dielectric layer to the landing pad in the BEOL structure, wherein the TSV has a first portion (250; FIG. 2; paragraph 0018) of a first width and a second portion (205; FIG. 2; paragraph 0018) of a second width and a discontinuous increase in width from the first width of the first portion to the second width of the second portion, the second width being at least 5% larger than the first width (FIG. 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Sio et al. in view of Hiblot et al. (US 20200373242 A1).
Regarding claim 2, Sio et al. teaches the semiconductor structure of claim 1, further comprising a landing pad (M1; FIG. 2; paragraph 0028) at the first metal level (M1; FIG. 2; paragraph 0028), wherein the landing pad has a width that is wider than a width of the first portion of the TSV (250; FIG. 2; paragraph 0018). Sio et al. does not teach the first portion of the TSV fully lands on the landing pad at the first metal level.
Hiblot et al. teaches a TSV (5a; FIG. 2; paragraph 0061) connected to a thinner rail (3a; FIG. 2; paragraph 0061) which fully land on a local interconnect (11a; FIG. 2; paragraph 0061).
Sio et al. and Hiblot et al. are both analogous to the claimed invention in that they involve semiconductor devices with TSVs. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Sio et al. so that the first portion of the TSV fully lands on the landing pad at the first metal level. This is a known aspect of the art that allows the voltage to connect into the TSV (paragraph 0061).
Regarding claim 16, Sio et al. teaches the semiconductor structure of claim 15, wherein the landing pad (M1; FIG. 2; paragraph 0028) is at one of one or more metal levels of the BEOL structure (M1; FIG. 2; paragraph 0028) and has a width that is wider than the first width of the first portion of the TSV (250; FIG. 2; paragraph 0018). Sio et al. does not teach the first portion of the TSV being directly in contact with the landing pad.
Hiblot et al. teaches a TSV (5a; FIG. 2; paragraph 0061) connected to a thinner rail (3a; FIG. 2; paragraph 0061) which fully land on a local interconnect (11a; FIG. 2; paragraph 0061).
Sio et al. and Hiblot et al. are both analogous to the claimed invention in that they involve semiconductor devices with TSVs. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Sio et al. so that the first portion of the TSV is directly in contact with the landing pad. This is a known aspect of the art that allows the voltage to connect into the TSV (paragraph 0061).
Claims 3, 6, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sio et al. in view of Andry et al. (US 20100178766 A1).
Regarding claim 3, Sio et al. teaches the semiconductor structure of claim 1. Sio et al. does not teach the structure further comprising a first guiding pad and a second guiding pad and a gap between the first guiding pad and the second guiding pad, wherein a width of the first portion of the TSV is substantially same as a width of the gap.
FIG. 3 of Andry et al. teaches a TSV (232; FIG. 3; paragraph 0018) constructed as an oxide shell (236; FIG. 3; paragraph 0017) surrounding a tungsten fill (238; FIG. 3; paragraph 0017).
Sio et al. and Andry et al. are both analogous to the claimed invention in that they involve semiconductor devices with TSVs. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Sio et al. so that it includes a first guiding pad and a second guiding pad and a gap between the first guiding pad and the second guiding pad, wherein a width of the first portion of the TSV is substantially same as a width of the gap. This is a known way to construct a TSV (paragraph 0017).
Regarding claim 6, the combination of Sio et al. in view of Andry et al. teaches the semiconductor structure of claim 3. Sio et al. does not teach the structure wherein the second portion of the TSV partially lands on the first and the second guiding pad such that the discontinuous increase in width of the TSV coincides with a location of the first and the second guiding pad.
FIG. 3 of Andry et al. teaches the thicker upper portion of the tungsten filling (238; FIG. 3; paragraph 0017) of the TSV (232; FIG. 3; paragraph 0018) lands on both sides of the oxide shell (236; FIG. 3; paragraph 0017), which surrounds the thinner lower portion.
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Sio et al. so that the second portion of the TSV partially lands on the first and the second guiding pad such that the discontinuous increase in width of the TSV coincides with a location of the first and the second guiding pad. This is a known aspect of the TSV structures from the filling (paragraph 0017).
Regarding claim 17, Sio et al. teaches the semiconductor structure of claim 1. Sio et al. does not teach the structure further comprising a first guiding pad and a second guiding pad and a gap between the first guiding pad and the second guiding pad, wherein the first width of the first portion of the TSV is substantially same as a width of the gap.
FIG. 3 of Andry et al. teaches a TSV (232; FIG. 3; paragraph 0018) constructed as an oxide shell (236; FIG. 3; paragraph 0017) surrounding a tungsten fill (238; FIG. 3; paragraph 0017).
Sio et al. and Andry et al. are both analogous to the claimed invention in that they involve semiconductor devices with TSVs. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Sio et al. so that it includes a first guiding pad and a second guiding pad and a gap between the first guiding pad and the second guiding pad, wherein a width of the first portion of the TSV is substantially same as a width of the gap. This is a known way to construct a TSV (paragraph 0017).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Andry et al. in view of Sio et al and further in view of Chuang et al. (US 20220037528 A1).
Regarding claim 8, Andry et al. teaches method of forming a semiconductor structure comprising:
forming a landing pad (236; FIG. 3; paragraph 0017) at a metal level of a back-end-of-line (BEOL) structure;
forming a first and a second guiding pad (236; FIG. 3; paragraph 0017) vertically above the landing pad;
forming a backside dielectric layer (240; FIG. 6; paragraph 0027) covering the first and the second guiding pad;
the second portion of the via opening (FIG. 3) exposing a portion of the first and the second guiding pad and a gap between the first and the second guiding pad;
creating a first portion of the via opening (FIG. 3) through the gap between the first and the second guiding pad, the first portion of the via opening exposing the landing pad; and
filling the via opening with a conductive material (238; FIG. 2; paragraph 0017) to form a through silicon via (TSV) (232; FIG. 3; paragraph 0018).
Andry et al. does not teach the landing pad being at a metal level of a back-end-of-line (BEOL) structure and the second portion of a via opening being in the backside dielectric layer.
FIG. 2 of Sio et al. teaches a metal line (ML1; FIG. 2; paragraph 0028) that acts as a landing pad for a TSV (205; FIG. 2; paragraph 0018) in a back-end-of-line (BEOL) interconnect structure. Sio et al. does not teach second portion of a via opening being in the backside dielectric layer.
FIG. 34 of Chuang et al. teaches a backside dielectric layer (292; FIG. 34; paragraph 0052) around a larger opening of a through via (312; FIG. 34; paragraph 0054).
Andry et al., Sio et al., and Chuang et al. are all analogous to the claimed invention in that they involve semiconductor devices with vias. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Andry et al. so that the landing pad is at a metal level of a back-end-of-line (BEOL) structure and the second portion of a via opening is in the backside dielectric layer. These are both known ways of constructing the device (Sio et al.: paragraph 0017; Chuang et al.: paragraph 0054).
Regarding claim 9, the combination of Andry et al. in view of Sio et al. and further in view of Chuang et al. teaches the method of claim 8. Andry et al. further teaches the method wherein the gap between the first and the second guiding pad (236; FIG. 3; paragraph 0017) is substantially aligned with the landing pad (236; FIG. 3; paragraph 0017) and a width of the gap is equal to or less than a width of the landing pad (236; FIG. 3; paragraph 0017).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Andry et al. in view of Sio et al., Chuang et al., and Gebara et al. (US 20110115004 A1).
Regarding claim 13, the combination of Andry et al. in view of Sio et al. and further in view of Chuang et al. teach the method of claim 8. Andry et al., does not teach the method further comprising forming a backside power distribution network in the backside dielectric layer and a C4 solder.
FIG. 2 of Sio et al. teaches a backside PDN (270; FIG. 2; paragraph 0018) as part of a backside dielectric layer (272; FIG. 2; paragraph 0018). Sio et al. does not teach forming a C4 solder.
FIG. 1 of Gebara et al. teaches c4 solders (100; FIG. 1; paragraph 0023).
Andry et al., Sio et al., Chuang et al., and Gebara et al. are all analogous to the claimed invention in that they involve semiconductor devices with vias. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Andry et al. to form a backside power distribution network in the backside dielectric layer and a C4 solder. These are known aspects of constructing PDNs (Sio et al.: paragraph 0022) and the c4 solder joints help keep the structure together (paragraph 0022).
Regarding claim 14, the combination of Andry et al. in view of Sio et al., Chuang et al., and Gabara et al. teach the method of claim 13. Andry et al. does not teach the method wherein the TSV is either connected to the BSPDN or connected to the C4 solder.
FIG. 2 of Sio et al. teaches a TSV (250; FIG. 2; paragraph 0018) backside PDN (270; FIG. 2; paragraph 0018).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Andry et al. to connect the TSV to a BSPDN. The connection of these structures help reduce IR drops (paragraph 0019).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Sio et al. in view of Gebara et al..
Regarding claim 20, Sio et al. teaches the semiconductor structure of claim 15, wherein the TSV (250; FIG. 2; paragraph 0018) is connected to the BSPDN (270; FIG. 2; paragraph 0018). Sio et al. does not teach the structure further comprising a C4 solder.
FIG. 1 of Gebara et al. teaches c4 solders (100; FIG. 1; paragraph 0023) connected to a TSV (120; FIG. 1; paragraph 0023).
Sio et al. and Gebara et al. are both analogous to the claimed invention in that they involve semiconductor devices with TSVs. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Sio et al. to include a C4 solder. The c4 solder joints help keep the structure together (paragraph 0022).
Allowable Subject Matter
Claims 4, 5, 10-12, 18, and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, the combination of Sio et al. in view of Andry et al. teaches the semiconductor structure of claim 3. Neither Sio et al. nor Andry et al. teach the structure wherein the first and the second guiding pad are horizontally aligned with one or more backside source/drain contacts of one or more transistors. None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify Sio et al. so that the first and the second guiding pad are horizontally aligned with one or more backside source/drain contacts of one or more transistors.
Regarding claim 5, the combination of Sio et al. in view of Andry et al. teaches the semiconductor structure of claim 3. Neither Sio et al. nor Andry et al. teach the structure wherein the first and the second guiding pad are horizontally aligned with one of one or more backside metal levels of the BSPDN. None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify Sio et al. so that the first and the second guiding pad are horizontally aligned with one of one or more backside metal levels of the BSPDN.
Regarding claim 10, the combination of Andry et al. in view of Sio et al. and further in view of Chuang et al. teach the method of claim 8. Neither Andry et al., Sio et al, nor Chuang et al. teach the method wherein forming the first and the second guiding pad comprises forming a first and a second dummy contact, the first and the second dummy contact are horizontally aligned with one or more backside source/drain contact of one or more transistors. None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify Andry et al. so that forming the first and the second guiding pad comprises forming a first and a second dummy contact, the first and the second dummy contact are horizontally aligned with one or more backside source/drain contact of one or more transistors.
Regarding claim 11, the combination of Andry et al. in view of Sio et al. and further in view of Chuang et al. teach the method of claim 8. Neither Andry et al., Sio et al, nor Chuang et al. teach the method wherein forming the first and the second guiding pad comprises forming a first and a second dummy metal line, the first and the second dummy metal line are horizontally aligned with one of one or more backside metal levels of a backside power distribution network. None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify Andry et al. so that forming the first and the second guiding pad comprises forming a first and a second dummy metal line, the first and the second dummy metal line are horizontally aligned with one of one or more backside metal levels of a backside power distribution network.
Regarding claim 12, the combination of Andry et al. in view of Sio et al. and further in view of Chuang et al. teach the method of claim 8. Neither Andry et al., Sio et al, nor Chuang et al. teach the method wherein creating the first portion of the via opening comprises etching a region in the gap between the first and the second guiding pad in an etch process that is selective to the first and the second guiding pad. None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify Andry et al. so that creating the first portion of the via opening comprises etching a region in the gap between the first and the second guiding pad in an etch process that is selective to the first and the second guiding pad.
Regarding claim 18, the combination of Sio et al. in view of Andry et al. teaches the semiconductor structure of claim 17. Sio et al. further teaches the structure further comprising one or more backside source/drain contacts of one or more transistors (220; FIG. 2; paragraph 0027). Neither Sio et al. nor Andry et al. teach the structure wherein the first and the second guiding pad and the one or more backside source/drain contacts have a coplanar surface.
None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify Sio et al. so that the first and the second guiding pad and the one or more backside source/drain contacts have a coplanar surface.
Regarding claim 19, the combination of Sio et al. in view of Andry et al. teaches the semiconductor structure of claim 17. Neither Sio et al. nor Andry et al. teach the structure wherein the BSPDN has a backside metal level, and wherein the first and the second guiding pad and the backside metal level has a coplanar surface.
FIG. 3 of Sisodia et al. (US 20220223514 A1) teaches backside metal rails (318; FIG. 3; paragraph 0022) powering a backside PDN (paragraph 0021). Sisoda et al. does not teach the structure wherein the first and the second guiding pad and the backside metal level has a coplanar surface.
None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify Sio et al. so that the first and the second guiding pad and the backside metal level has a coplanar surface.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Xie et al. (US 20220399224 A1) concerns manufacturing a semiconductor device with nano through-silicon vias and a backside power distribution network. Sahu et al. (US 20220415742 A1) teaches microelectronic assemblies including micro TSVs, backside PDNs, and BEOLs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.A.V./ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817
Prosecution Insights