DETAILED ACTION
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
1. Claims 1-2 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Sakaguchi (USPN 2022/0190815)
Regarding claim 1, Sagaguchi discloses an overcurrent protection circuit (a protection circuit shown in figures 1, 3), comprising:
a first mirror transistor (a first sensing transistor 13, see figure 3) configured to be driven by a first drive signal (a first signal VG from a driver 12), common to a first output transistor (an output transistor 11), so as to pass a first mirror current (a first mirror current Is1);
a second mirror transistor (a second mirror transistor 41) configured to be driven by a second drive signal (a second drive signal 40-4) so as to pass a second mirror current (a second mirror current Is2);
a resistor (each transistor 11, 13, 41 includes an internal gate resistor) configured to be connected between a control terminal of each of the first output transistor (11) and the first mirror transistor (13) and a control terminal of the second mirror transistor (41); and
a current restriction unit (30a) configured to control the first drive signal (VG) such that a sense current (a total sensed current flowing through a sensing resistor 14), which is a total of the first mirror current (Is1) and the second mirror current (Is2), is restricted to values equal to or less than a predetermined upper limit value (e.g. see par. 0035, 0060-0061).
Regarding claim 2, Sagaguchi discloses wherein the current restriction unit (30a) includes:
a sense resistor (14) configured to convert the sense current to a sense voltage; and an operational amplifier (32) configured to regulate the first drive signal in accordance with the sense voltage.
2. Claims 1, 4, 5, 10 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chen (USPN 2010/0213908).
Regarding claim 1, Yahagi discloses an overcurrent protection circuit (a protection circuit 100 shown in figure 5), comprising:
a first mirror transistor (a first mirror transistor MP3, see figure 5) configured to be driven by a first drive signal (a first signal VG from a driver 10), common to a first output transistor (an output transistor PT), so as to pass a first mirror current (a first mirror current I7, see par. 0031);
a second mirror transistor (a second mirror transistor MP10) configured to be driven by a second drive signal (a second drive signal from switch SW1) so as to pass a second mirror current (a second mirror current I9);
a resistor (each transistor PT, MP3, MP10 includes a gate resistor) configured to be connected between a control terminal of each of the first output transistor (PT) and the first mirror transistor (MP3) and a control terminal of the second mirror transistor (MP10); and
a current restriction unit (20C, 30C) configured to control the first drive signal (VG) such that a sense current (I8), which is a total of the first mirror current (I7) and the second mirror current (I9) (see par. 0039), is restricted to values equal to or less than a predetermined upper limit value (e.g. see par. 0038-0040).
Regarding claim 4, Chen discloses (the gate resistor of transistor PT, MP3, MP10) wherein the resistor has a resistance value of several tens to several hundreds kΩ (the transistors PT, MP3, MP10 includes the gate resistor of several tens ohm).
Regarding claim 5, Chen discloses a power supply device ( see figure 5), comprising: the first output transistor (PT) configured to be connected between an input terminal (Vin) for an input voltage and an output terminal (OUT) for an output voltage so as to be driven by the first drive signal (VG);
an output feedback circuit (R1, R2, 10) configured to generate the first drive signal (VG) in accordance with a difference between the output voltage, or a feedback voltage in accordance with the output voltage, and a predetermined reference voltage (Vref1, see par. 0018); and the overcurrent protection circuit.
Regarding claim 10, Chen discloses wherein the output feedback circuit includes an error amplifier (see par. 0018) configured to generate the first drive signal (VG) in accordance with the difference between the output voltage or the feedback voltage and the reference voltage (Vref1) (see par. 0018).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (USPN 2010/0213908) in view of Ma et al (USPN 2019/0279977).
Regarding claim 3, Chen discloses the first mirror transistor (MP3), the second mirror transistor (MP10), and the first output transistor (PT)(see figure 5), but does not explicitly disclose size as claimed.
Ma discloses a protection circuit device comprises a first mirror transistor (412), a second mirror transistor (414), and a first output transistor (408), wherein the first mirror transistor (412) and the second mirror transistor (414) are smaller in size than the first output transistor (408) (see par. 0027).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the sizes of first and second mirror transistors which are smaller that a size of the output transistor as disclosed by Ma in order to save silicon area and power.
Allowable Subject Matter
4. Claims 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY NGUYEN whose telephone number is (571)272-2054. The examiner can normally be reached M-F 8:00AM-4:30PM.
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/DANNY NGUYEN/ Primary Examiner, Art Unit 2838