DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 11/20/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
An integrated circuit of claims 2, 3, 6, 7, 9, 10, 13-17,
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Gao (US 20180083440 A1).
Regarding claim 1, Gao teaches an electrostatic discharge (ESD) clamp circuit (abstract, electrostatic discharge (ESD) protection and methods), comprising:
a discharge circuit (e.g. circuit comprising NFET 30, fig.1) to discharge a current flow during a transient ESD voltage event ([0031], positive ESD by activation of the transistor 30 and to a negative ESD passing through the parasitic diode effect of the transistor 30);
a disable input (i.e. node 54, fig.1) to receive a disable input signal ([0038], application of a signal on the associated pin out); and
a disable circuit (e.g. circuit comprising device 50, fig.1) to, based upon the disable input signal, selectively disable the discharge circuit ([0038], the disable device 50 is high-effective);
wherein:
when the disable input signal is a first logic state, the disable circuit is to allow the discharge circuit to be enabled ([0038], unconnected … the disable device 50 is inoperative, and the ESD protection circuit 20 is operative fully); and
when the disable input signal is in a second logic state, the disable circuit is to disable the discharge circuit ([0038], the disable device 50 is high-effective).
Regarding claim 2, Gao teaches the electrostatic discharge clamp circuit of claim 1, wherein the disable input signal is at the second logic state by default after an integrated circuit containing the electrostatic discharge clamp circuit is initialized ([0038], the disable device 50 is inoperative, and the ESD protection circuit 20 is operative fully to naturally protect the IC 10).
Regarding claim 3, Gao teaches the electrostatic discharge clamp circuit of claim 1, wherein the disable input signal is at the first logic state while an integrated circuit containing the electrostatic discharge clamp circuit is powered off ([0038], unconnected, such as when the IC is not associated with a printed circuit board (PCB), the disable device 50 is inoperative).
Regarding claim 4, Gao teaches the electrostatic discharge clamp circuit of claim 1, comprising: a filter to stabilize the disable input signal ([0038], The node 54 couples to a pin out (not depicted) of the IC 10) (it is necessarily true that the pin out has a resistance that will act as filter).
Regarding claim 5, Gao teaches the electrostatic discharge clamp circuit of claim 1, wherein: the disable circuit includes a switch (e.g. PFET 50, fig.1); and the disable input signal controls a state of the switch ([0036], node 54 couples to a pin out … such that a state of the device 50 may be effected by application of a signal on the associated pin out).
Regarding claim 6, Gao teaches the electrostatic discharge clamp circuit of claim 1, wherein the disable input signal is at the first logic state by default before an integrated circuit containing the electrostatic discharge clamp circuit is initialized ([0038], such as when the IC is not associated with a printed circuit board (PCB), the disable device 50 is inoperative).
Regarding claim 7, Gao teaches the electrostatic discharge clamp circuit of claim 1, wherein the disable circuit is coupled to an input voltage (e.g. 50 is coupled to Vdd, fig.1) and a ground (e.g. 50 is coupled to Vss via 34, fig.1) of an integrated circuit ([0019], Packages for an IC may and typically have several pin outs including at least a first power rail pin (Vdd) and a second power rail pin (Vss)).
Regarding claim 8, Gao teaches an apparatus (e.g. fig.1), comprising:
an input voltage pin (e.g. pin comprising Vdd power supply rail 22, fig.1);
a ground pin (e.g. pin comprising grounded Vss power supply rail 24, fig.1);
a discharge circuit (e.g. circuit comprising NFET 30, fig.1) coupled between the input voltage pin and the ground pin (e.g. 30 is inbetween Vdd and Vss, fig.1), the discharge circuit to discharge a current flow during a transient ESD voltage event ([0031], positive ESD by activation of the transistor 30 and to a negative ESD passing through the parasitic diode effect of the transistor 30), wherein the discharge circuit includes a first switch (i.e. NFET 30, fig.1);
a disable input (i.e. node 54, fig.1) to receive a disable input signal ([0038], application of a signal on the associated pin out); and
a disable circuit (e.g. circuit comprising device 50, fig.1) coupled between the discharge circuit and the disable input to disable the discharge circuit (e.g. 50 is between node 54 and 30, fig.1), wherein the disable circuit includes a second switch (e.g. transistor 50, fig.1); and
wherein:
when the disable input signal is a first logic state, the disable circuit is to allow the discharge circuit to be enabled ([0038], unconnected … the disable device 50 is inoperative, and the ESD protection circuit 20 is operative fully); and
when the disable input signal is in a second logic state, the disable circuit is to disable the discharge circuit ([0038], the disable device 50 is high-effective).
Regarding claim 9, it is rejected for the same reasons as stated above for claim 2.
Regarding claim 10, it is rejected for the same reasons as stated above for claim 3.
Regarding claim 11, it is rejected for the same reasons as stated above for claim 4.
Regarding claim 12, it is rejected for the same reasons as stated above for claim 5.
Regarding claim 13, it is rejected for the same reasons as stated above for claim 6.
Regarding claim 14, the method is rejected for the same reasons as stated above for claim 8.
Regarding claim 15, the method is rejected for the same reasons as stated above for claim 2.
Regarding claim 16, the method is rejected for the same reasons as stated above for claim 3.
Regarding claim 17, the method is rejected for the same reasons as stated above for claim 6.
Regarding claim 18, the method is rejected for the same reasons as stated above for claim 4.
Regarding claim 19, Gao teaches the method of claim 14, wherein disabling the discharge circuit and enabling the disable circuit when the disable input signal is at the second logic state includes: disabling a first switch of the discharge circuit ([0036], inhibiting activation of the transistor 30); and enabling a second switch of the disable circuit ([0036], As a high-effective switch, the device 50).
Regarding claim 20, Gao teaches the method of claim 14, wherein enabling the discharge circuit and disabling the disable circuit when the disable input signal is at the first logic state includes: enabling a first switch of the discharge circuit ([0038], the ESD protection circuit 20 is operative fully to naturally protect the IC 10); and disabling a second switch of the disable circuit ([0038], disable device 50 is inoperative).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Gao (US 20170302066 A1) fig.1, Rupp (US 20210257833 A1) fig.3, Sakihama (US 20050030688 A1) fig.6 and Dai (US 20200321331 A1) fig.2.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SREEYA SREEVATSA whose telephone number is (571)272-8304. The examiner can normally be reached M-F 8am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SREEYA SREEVATSA/ Primary Examiner, Art Unit 2838 12/05/2025