DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/5/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Pulvirenti (US 6,362,697, of record) in view of Sodini et al. (“Lecture 12: Digital Circuits (II) MOS Inverter Circuits”, of record and hereinafter “Sodini”).
Claim 1: Pulvirenti discloses a relaxation oscillator (Figs.5-6), comprising:
a first transistor (P1), through which a constant current is made to flow (mirrored via P0 and 6);
a first capacitor (C1), which is charged by a current from the first transistor (from P1; see Fig.5);
a second transistor (N3), which draws a charge of the first capacitor (according to Q; see Fig.5);
a third transistor (P2), through which a constant current is made to flow (mirrored via P0 and 6; see Fig.5-6);
a second capacitor (C2), which is charged by a current from the third transistor (from P2);
a fourth transistor (N4), which draws a stored charge of the second capacitor (according to QN);
a fifth transistor (N1), which receives the charging voltage of the first capacitor (at C1) at a control end (gate) and is turned on/off (see Figs.5-6 and col.5,8-11); and
a sixth transistor (N2), which receives the charging voltage of the second capacitor (at C2) at a control end (gate) and is turned on/off (see Figs.5-6 and col.5,12-17);
a flip-flop (cross-coupled NAND gates, being an RS flip flop; see Fig.5), whose state changes from a first state to a second state when a charging voltage of the first capacitor reaches a predetermined value (see Figs.5-6 and col.5,8-11), and changes from the second state to the first state when a charging voltage of the second capacitor reaches a predetermined value (see Figs.5-6 and col.5,12-17), the flip-flop causing the second transistor to be turned off and the fourth transistor to be turned on in the first state (N3 being off and N4 being on in the first state), and causing the second transistor to be turned on and the fourth transistor to be turned off in the second state (N3 being on and N4 being off in the second state; see col.5,8-17), wherein the state of the flip-flop changes as the fifth transistor and the sixth transistor are turned on/off (see Figs.5-6 and col.5,8-17) and
the relaxation oscillator outputting a signal of a predetermined frequency from the flip-flop (Q and QN; see Figs.4-6 and col.5,18-31).
Pulvirenti further discloses NMOS inverter structures N1, I3/P3 and N2, I4/P4 providing an output to the flip flop (FF) based on voltages at each capacitor (XA, XB; see Fig.4, which corresponds to P3, N1 and P4, N2 of Fig.5). Pulvirenti discloses that the first current source (I3/P3) being connected in series to the fifth transistor (N1), and the voltage of a connection point with the fifth transistor changing as the fifth transistor is turned on/off (input to R; see Figs.5-6 and col.5,8-17); the state of the flip-flop changes according to the voltage change of the connection point between the current source and the fifth transistor (see Figs.5-6 and col.5,8-17); the relaxation oscillator comprises an second current source (I4/P4), the second current source being connected in series to the sixth transistor (in series with N2), and the voltage of a connection point with the sixth transistor changing as the sixth transistor is turned on/off (see Figs.5-6 and col.5,8-17) and the state of the flip-flop changes according to the voltage change of the connection point between the second current source and the sixth transistor (see Figs.5-6 and col.5,8-17). Pulvirenti does not disclose the “first resistor” and the “second resistor” of claim 1.
Sodini discloses an alternative design of an NMOS inverter (pgs.2-3), alternative to the current source inverter of Pulvirenti (shown on pg.5 of Sodini), where the current source is replaced with a load resistor (R, of pg.2). Sodini discloses that the use of a load resistor is a design trade-off between speed, noise margin (see pg.3) and power consumption (pg.8). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have substituted the current sources within the inverter of Pulvirenti (i.e. P3 and P4) with first and second load resistors, as a design trade-off between speed, noise margin, and power consumption. Further, as both designs of an NMOS inverter provide an identical function of inverting a logic value provided to the input, the results of substituting the current source of the NMOS inverter with a resistor would have been predictable to one of ordinary skill in the art. Therefore, it further would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have substituted the current sources P3 and P4 of Pulvirenti with resistors as disclosed by Sodini as the simple substitution of one known element for another to obtain predictable results.
Claim 4: Pulvirenti discloses wherein the relaxation oscillator comprises a tenth transistor (P3), through which a constant current is made to flow (mirrored from P0), the tenth transistor being connected in series to the fifth transistor (in series with N1; see Fig.5), and the voltage of a connection point with the fifth transistor changing as the fifth transistor is turned on/off (input to R; see Figs.5-6 and col.5,8-17); the state of the flip-flop changes according to the voltage change of the connection point between the tenth transistor and the fifth transistor (see Figs.5-6 and col.5,8-17); the relaxation oscillator comprises an eleventh transistor (P4), through which a constant current is made to flow (mirrored from P0), the eleventh transistor being connected in series to the sixth transistor (in series with N2), and the voltage of a connection point with the sixth transistor changing as the sixth transistor is turned on/off (see Figs.5-6 and col.5,8-17) and the state of the flip-flop changes according to the voltage change of the connection point between the eleventh transistor and the sixth transistor (see Figs.5-6 and col.5,8-17).
Claim 6: Pulvirenti discloses a 0th transistor (P0), of which a diode-connected control end (gate, which is diode-connected; see Figs.5 and 6) is connected to control ends of the first transistor and the third transistor (see Figs.5 and 6); and a 0th resistor (R0), which is connected in series to the 0th transistor (via N5); wherein the magnitudes of a constant current flowing through the first transistor and a constant current flowing through the second transistor are adjusted by a resistance value of the 0th resistor (P1-P4 being mirrored from P0, and P0 having a magnitude current based on R0, thus the current flowing through P1-P4 are adjusted based on a resistance value of R0; see col.6,8-14 and col.5,39-47).
Response to Arguments
Applicant's arguments filed 12/5/2025 with respect to the rejection of claims 1, 3, and 6 under 35 U.S.C. 103 over Pulvirenti in view of Sodini have been fully considered but they are not persuasive.
Applicant argues, “In the embodiments of the subject application, each resistor is connected in series with a corresponding sensing transistor … and defines a voltage division point used by the flop-flop to determine its switching threshold”.
However, the claims do not specifically require any specific function related to determining a flip-flop’s switching threshold. The specific language of claim 1 recites “the state of the flip-flop changes according to the voltage change of the connection point between the first/second resistor and the fifth/sixth transistor”. As this is the function of an NMOS inverter with a load resistor, where the voltage between the drain and the load resistor changes according to the gate voltage, the language of the claim is met by substituting the current source of Pulvirenti with a load resistor.
Applicant next argues, “Sodini does not change the state of a flip-flop, let alone the state of a flip-flop changing according to the voltage change of a connection point between the resistor and the transistor”.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Specifically, the combination of Pulvirenti and Sodini discloses an output of an NMOS inverter being provided to a flip-flop circuit, as discussed above, as the node between the drain of the NMOS transistor and the load resistor provides an inverted logic voltage provided at the gate of said NMOS transistor.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Applicant argues that C1 of Pulvirenti is connected to the gate of N1 whereas CL of Sodini is connected to a connection point between the resistor. However, in the combination of Pulvirenti and Sodini, the location of C1/C2 is not altered. Rather, current sources P3/P4 are simply substituted with load resistors, an alternative NMOS inverter design as disclosed by Sodini.
Applicant next argues that there is no motivation to modify Pulvirenti. The examiner respectfully disagrees, as Sodini discloses the design tradeoffs between a load resistor and current source in an NMOS inverter, specifically between speed, noise margin and power consumption. Further, as an NMOS inverter provides an inverted output whether a load resistor or current source is utilized, the results of substituting a current source with a load resistor would have been predictable to one of ordinary skill in the art. Therefore, it further would have been obvious as the simple substitution of one known element for another to obtain predictable results. See MPEP 2143.I.B.
Applicant next argues that substituting a load resistor for the current sources of Pulvirenti would significantly affect the behavior of the latch and render Pulvirenti’s circuit inoperative. However, Applicant does not further elaborate on how a simple substitution of one known NMOS inverter design including a current source with another including a load resistor would affect the behavior of the latch of Pulvirenti and/or render the circuit operable. As an NMOS inverter provides an identical function of inverting an input logic voltage, whether a load resistor or current source design is implemented, the examiner respectfully disagrees that the function of the latch would be affected and/or the circuit would be inoperable.
Finally, Applicant argues that the claimed invention provides the technical effects regarding high precision oscillation and argues that parts of Sodini that teach such a technical effect are not specified. However, the examiner notes that the claims do not specifically require any “high-precision oscillation”, such a feature is disclosed by Pulvirenti (see col.5,32-35).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN JOHNSON whose telephone number is (571)270-1264. The examiner can normally be reached Monday - Friday, 9:00 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menna Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RYAN JOHNSON/Primary Examiner, Art Unit 2849