Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office acknowledges receipt of the following items from the Applicant:
Information Disclosure Statement (IDS) filed on 4/22/24 was considered.
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-3 and 11-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyatake et al, U.S. Patent Application No. 2020/0312384.
With regard to claim 1 and 11, Miyatake discloses an apparatus comprising: a plurality of prime memory cell rows and a plurality of redundant memory cell rows (page 1, [0014], line 9-16); and row decoder circuitry (fig. 1, 130) configured to receive an access command and a row address (page 1, [0013], line 22-25), wherein the row decoder circuitry (fig. 1, row decoder 130) is configured to, in response to a determination that the row address matches a defective row address (page 1, [0014]), cause initiation of a threshold voltage compensation operation concurrently for both of a prime memory cell row of the plurality of prime memory cell rows and a redundant memory cell row of the plurality of redundant memory cell rows (page 2, [0016]-[0017]).
With regard to claim 2 and 12, Miyatake discloses wherein the plurality of prime memory cell rows discloses, line and the plurality of redundant memory cell rows are included in a same mat (page 1, [0014], line 9-12).
With regard to claim 3 and 13, Miyatake discloses wherein the plurality of prime memory cell rows and the plurality of redundant memory cell rows are included in different sections of a bank (fig. 6, shows plurality of redundant Mbit (610( 0) and redundant Mbit (630)(1) are at located at both end of the primary memory Mbit(610(0)… Mbit(610(6) sections, thus they are in different section of the bank).
Allowable Subject Matter
Claim 4-10 and 14-20 are objected as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record does not show the limitation of wherein the row decoder circuitry comprises a plurality of fuse latch and comparator circuits each corresponding to a respective one of the plurality of redundant memory cell rows, and wherein each fuse latch and comparator circuit is configured to provide a match signal when a received row address matches a stored defective row address.
Double Patent Rejection
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claim1-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-20 of Akamatsu, U.S. Patent No. 11,967.356. Although the conflicting claims are not identical, they are not patentably distinct from each other because of the reasons set forth below.
With regard to claim 1, 2, 11 and 12 are similar to claim 1 of the 11,967,356 patent. Similar to the claimed invention, claim 1 of patent ‘356 discloses an apparatus comprising: a plurality of prime memory cell rows; a plurality of redundant memory cell rows; and row decoder circuitry configured to receive an access command and a row address, wherein the row decoder circuitry is configured to, in response to a determination that the row address matches a defective row address, cause initiation of a threshold voltage compensation operation concurrently for both of a prime memory cell row of the plurality of prime memory cell rows and a redundant memory cell row of the plurality of redundant memory cell rows (claim 1 and 11); wherein the plurality of prime memory cell rows and the plurality of redundant memory cell rows are included in a same mat (claim 2 and 12)
With regard to claim 3 and 13 are similar to claim 7 of patent 11,967,356 patent. Similar to the claimed invention, claim 7 of patent ‘356 discloses wherein the plurality of prime memory cell rows and the plurality of redundant memory cell rows are included in different sections of a bank.
With regard to claim 4 and 14 are similar to claim 2 of the 11,967,356 patent. Similar to the claimed invention, claim 2 of patent ‘356 discloses wherein the row decoder circuitry comprises a plurality of fuse latch and comparator circuits each corresponding to a respective one of the plurality of redundant memory cell rows, and wherein each fuse latch and comparator circuit is configured to provide a match signal when a received row address matches a stored defective row address.
With regard to claim 5 and 15 are similar to claim 3 of the 11,967,356 patent. Similar to the claimed invention, claim 3 of patent ‘356 discloses wherein the row decoder circuitry further comprises a logic tree configured to provide a hit signal based on the match signal, and wherein the row decoder circuitry is configured to stop the threshold voltage compensation operation on the prime memory cell row responsive to the hit signal.
With regard to claim 6 and 16 are similar to claim of claim 4 of the 11,967,356 patent. Similar to the claimed invention, claim 4 of patent ‘356 discloses wherein the hit signal is delayed relative to the match signal.
With regard to claim 7 and 17 are similar to claim 5 of the 11,967,356 patent. Similar to the claimed invention, claim 5 of patent ‘356 discloses wherein the logic tree includes cascading XOR gates to determine whether a respective match signal of a fuse latch and comparator circuit of the plurality of fuse latch and comparator circuits is set.
With regard to claim 8 and 18 are similar to claim 2 of the 11,967,356 patent. Similar to the claimed invention, claim 2 of patent ‘356 discloses wherein the match signal is provided responsive to an initial detection of a redundant row address.
With regard to claim 9 and 19 are similar to claim 9 of the 11,967,356 patent. Similar to the claimed invention, claim 9 of patent ‘356 discloses wherein, when no match signal is generated for the received row address, the threshold voltage compensation operation is not initiated on the redundant memory cell row.
With regard to claim 10 and 20 are similar to claim 6 of the 11,967,356 patent. Similar to the claimed invention, claim 6 of patent ‘356 discloses wherein a fuse latch and comparator circuit of the plurality of fuse latch and comparator circuits includes respective fuse latches configured to store a respective defective prime address received from a fuse array.
eTerminal Disclaimer
The USPT© internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to
http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp
Claims 1-20 would be allowable if an eTerminal Disclaimer signed and filed by an attorney or agent of record to overcome the obviousness-type double patenting rejection and overcome the rejected under 35 U.S.C. 102(a)(1) set forth above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicants' disclosure. Song et al (5959906) discloses a memory device having in combination with other features, a semiconductor memory device is shown that includes a normal memory cell array including a plurality of memory cells specified by 2n word lines and a plurality of column bit lines where an externally input n-bit row address is decoded to activate one of the 2n word lines. The semiconductor memory device further includes a redundant row fuse decoder that includes a plurality of n-bit address fuse portions each of which can be selectively coded to respond to an n-bit defective row address value in the externally input n-bit row address which corresponds to a word line in the normal memory cell array that includes a defective memory cell. The semiconductor memory device further includes a redundant memory cell array including a plurality of rows of memory cells which can be activated by one of the n-bit address fuse portions in response to the defective row address coded into the n-bit address fuse portion; and
Gadamestty (US 2023/207033) discloses method used to perform concurrent compensation in a memory array. The example method may include decoding a prime row address corresponding to a respective prime memory cell row of a first row section of a memory array mat to provide a prime section signal, and in response to a determination that the prime row address matches a defective prime row address, providing a redundant section signal corresponding to a respective redundant memory cell row of a second row section of the memory array mat. In response to the prime section signal, initiating a first threshold voltage compensation operation on first sensing circuitry coupled to the first row section; and in response to the redundant section signal indicating a defective prime row, initiating a second threshold voltage compensation operation on second sensing circuitry coupled to the second row section concurrent with the first threshold voltage compensation operation.
When responding to the office action, Applicants' are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
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/CONNIE C YOHA/Primary Examiner, Art Unit 2825