DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of elects Invention I, drawn to a semiconductor device, Species 1, corresponding to the embodiment of FIG. 3, 1, 3-6, 8, 11, 12, 14, 15, 19, and 20 in the reply filed on 06/30/2026 is acknowledged. The traversal is on the ground(s) that traverses the restriction between Inventions I and II on the grounds that the Examiner has not met the burden of establishing that restriction is proper. The Examiner asserts that the product as claimed can be made by a materially different process, citing the
example of selectively epitaxially growing an epitaxial layer to form a trench structure rather than epitaxially growing and etching. However, this example does not constitute a materially different process sufficient to establish distinctness under MPEP § 806.05(f). The alternative process identified by the Examiner would still require the same fundamental steps of forming an epitaxial layer and creating the claimed trench structure comprising first trenches extending in a first direction and a second trench extending in a second direction disposed in a cross manner. The resulting structural elements-the cross-trench configuration, the gate, the interlayer dielectric layer with a contact hole extending perpendicular to the first trenches, the source, and the drain would be the same regardless of whether the trench is formed by etching or selective epitaxial growth.
Furthermore, the Examiner has not demonstrated a serious search or examination burden, as the product and process claims share substantially overlapping structural limitations that would be located through the same prior art search in the same classes and subclasses.
This is not found persuasive because
Regarding (i), inventions are distinct if the product as claimed can be made by another and materially different process (See MPEP § 806.05(f)). In the instance case, the device is made by etching the first epitaxial layer to form gate trenches and etching the interlayer dielectric layer to form contact hole as recited in claim 16. However, instead of the etching step, the gate trenches can be made by selective growth over a mask pattern and contact hole can be made by selective deposition through a mask pattern. As such, the product can be made by another materially different process and the inventions as claimed are distinct .
Regarding (ii), there exist a serious search burden because the inventions require separate searches due to their different classification areas. Furthermore, search of the product would not require searching for the specific method steps, e.g. “epitaxially growing”, “etching” as recited in claim 16 and “ion implantation process as recited in claim 17.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-6, 8, 11, 14, 15, 19, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 19 reciting “a first that is … spaced apart by a gate dielectric layer” render the claim indefinite. It is unclear what the gate is spaced apart from.
Claim 2 recites “two adjacent trench structures” is unclear and indefinite as claim 1 only recite a single trench structure. Claim 2 recites trench structures which is 2 more. As such it is unclear and indefinite.
Claim 2 recites “at least one first trench” is unclear and indefinite if the “at least one first trench” is a subset of the “a plurality of first trenches” recited in claim 1.
Claim 8 recites “two adjacent first trenches” is unclear and indefinite if the “at least one first trench” is a subset of the “a plurality of first trenches” recited in claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-6, 8, 11, 12, 14, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Saggio et al. 20200044077 in view of REN et al. 20230078222.
PNG
media_image1.png
488
759
media_image1.png
Greyscale
PNG
media_image2.png
449
749
media_image2.png
Greyscale
Regarding claim 1, fig. 3F of Saggio discloses a semiconductor device, comprising:
an N-type semiconductor substrate 64;
an epitaxial layer 66/68/70 (fig. 3A and par [0063] - epitaxial), disposed on the semiconductor substrate;
a trench structure (fig. 3B), disposed at the epitaxial layer, wherein the trench structure comprises: a plurality of first trenches (74a/b) that extend in a first direction Y parallel to a plane on which the semiconductor substrate is located and are arranged at intervals in a second direction X parallel to the plane on which the semiconductor substrate is located (par [0065]); and
a gate 82a that is filled and disposed in the trench structure and is spaced apart by a gate dielectric layer 80a;
an interlayer dielectric layer 86 that is disposed on the gate and covers the gate, wherein the interlayer dielectric layer comprises a contact hole 88 that extends in the second direction and exposes a partial region of the epitaxial layer, wherein a projection of the contact hole in a third direction perpendicular to the plane on which the semiconductor substrate is located does not overlap the gate, and wherein the first direction, the second direction, and the third direction are set in a cross manner;
a source 50 that is disposed at the interlayer dielectric layer and is in contact, through the contact hole, with the epitaxial layer exposed by the contact hole; and
a drain 52 that is disposed on a side of the semiconductor substrate and away from the epitaxial layer.
Saggio does not disclose a second trench that extends in the second direction, wherein the second trench and each of the plurality of first trenches are disposed in a cross manner and communicate with each other.
PNG
media_image3.png
395
502
media_image3.png
Greyscale
However, FIG. 1 of REN schematically shows a trench-gate MOSFET cell 000 comprising a trench structure, wherein the trench structure comprises: a plurality of first trenches (note fig. 1 is for cell 000 and there are more than one cell formed on the substrate) that extend in a first direction Y parallel to a plane on which a semiconductor substrate is located and are arranged at intervals in a second direction; and a second trench that extends in the second direction, wherein the second trench and each of the plurality of first trenches are disposed in a cross manner and communicate with each other.
Note the trench structure of REN has benefit of more gate to channel surface for more current flow to create a more powerful trench-gate power MOSFET.
As such it would have been obvious to form a device of Saggio further comprising a second trench that extends in the second direction, wherein the second trench and each of the plurality of first trenches are disposed in a cross manner and communicate with each other such as taught by REN in order to produce more gate to channel surface for more current flow to create a more powerful trench-gate power MOSFET.
Regarding claim 3, fig. 2 of Saggio discloses wherein the epitaxial layer comprises a first N-type semiconductor region (region next to 34a), a second N-type semiconductor region (region in direct contact with 38), a first P-type semiconductor region 38, and a source region 40 that are sequentially disposed on the semiconductor substrate; the trench structure extends to the first N-type semiconductor region in the third direction perpendicular to the plane on which the semiconductor substrate is located; and the contact hole exposes a partial region of the source region.
Regarding claim 4, fig. 2 of Saggio discloses wherein the epitaxial layer further comprises: a second P-type semiconductor region 44a that is disposed in the first N-type semiconductor region, is located below the trench structure, and is connected to the source.
Regarding claim 5, fig. 2 of Saggio discloses wherein the epitaxial layer further comprises: a third P-type semiconductor region (region of 38 direct next to the trench) that is disposed on at least one side wall of the trench structure and is in contact with the second P-type semiconductor region; and a fourth P-type semiconductor region, wherein the fourth P-type semiconductor region (interface P region with N of layer 40) and the source region are disposed at a same layer (interface layer), and wherein the fourth P-type semiconductor region and the third P-type semiconductor region are disposed in a one-to-one correspondence and are in contact with each other.
Regarding claim 6, fig. 2 of Saggio wherein each of the plurality of first trenches has a first side wall and a second side wall that are disposed opposite to each other in the first direction; and the third P-type semiconductor region is disposed on the first side wall and/or the second side wall of at least one of the plurality of first trenches, or the fourth P-type semiconductor region is in contact with the source through the contact hole.
Regarding claim 8, Saggio does not explicitly disclose wherein a width of the fourth P-type semiconductor region is equal to a width of the at least one first trench; and a trench spacing between two adjacent first trenches is equal to a width of the source region.
However, changes in size, proportion, or shape in MPEP § 2144.04 (IV), note that the court has held that if a claimed device differs from prior art only in relative dimensions and would perform the same as the prior art device, it is not patentably distinct. This principle was established in Gardner v. TEC Syst., Inc., 725 F.2d 1338 (Fed. Cir. 1984), where the court held that mere recitation of relative dimensions does not confer patentability if the performance remains unchanged.
As such it would have been obvious to form a device comprising disclose wherein a width of the fourth P-type semiconductor region is equal to a width of the at least one first trench; and a trench spacing between two adjacent first trenches is equal to a width of the source region to meet the applicant design requirement.
Regarding claim 11, Saggio does not explicitly discloses wherein doping concentrations of the second P-type semiconductor region, the third P-type semiconductor region, and the fourth P-type semiconductor region are each greater than a doping concentration of the first P-type semiconductor region.
However, changes in size, proportion, or shape in MPEP § 2144.04 (IV), note that the court has held that if a claimed device differs from prior art only in relative dimensions and would perform the same as the prior art device, it is not patentably distinct. This principle was established in Gardner v. TEC Syst., Inc., 725 F.2d 1338 (Fed. Cir. 1984), where the court held that mere recitation of relative dimensions does not confer patentability if the performance remains unchanged.
As such it would have been obvious to form a device comprising disclose wherein doping concentrations of the second P-type semiconductor region, the third P-type semiconductor region, and the fourth P-type semiconductor region are each greater than a doping concentration of the first P-type semiconductor region to meet the applicant design requirement.
Regarding claim 14, Saggio does not explicitly disclose wherein a doping concentration of the semiconductor substrate is greater than a doping concentration of the second N-type semiconductor region; and the doping concentration of the second N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region.
However, changes in size, proportion, or shape in MPEP § 2144.04 (IV), note that the court has held that if a claimed device differs from prior art only in relative dimensions and would perform the same as the prior art device, it is not patentably distinct. This principle was established in Gardner v. TEC Syst., Inc., 725 F.2d 1338 (Fed. Cir. 1984), where the court held that mere recitation of relative dimensions does not confer patentability if the performance remains unchanged.
As such it would have been obvious to form a device comprising disclose disclose wherein a doping concentration of the semiconductor substrate is greater than a doping concentration of the second N-type semiconductor region; and the doping concentration of the second N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region to meet the applicant design requirement.
Regarding claim 15, par [0059] of Saggio discloses wherein materials of the semiconductor substrate and the epitaxial layer are silicon carbide (SiC).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Saggio and REN in view of OKUMURA et al. 20180033885.
Regarding 12, Saggio and REN disclose claim 5, but do not disclose wherein a projection of the second P-type semiconductor region in the third direction covers the trench structure and the third P-type semiconductor region.
PNG
media_image4.png
448
623
media_image4.png
Greyscale
However, fig. 1 of OKUMURA wherein a projection of the second P-type semiconductor region 11 in the third direction covers a trench structure and the third P-type semiconductor region in order that high electric field at a portion of the gate insulating film 8 along the bottom of the trench 7 may be suppressed.
In view of such teaching, it would have been obvious to form a device comprising wherein a projection of the second P-type semiconductor region in the third direction covers the trench structure and the third P-type semiconductor region such as taught by OKUMURA in order that high electric field at a portion of the gate insulating film along the bottom of the trench may be suppressed.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Saggio and REN in view of Akama et al. 20080252242.
Regarding claim 19, fig. 3F of Saggio discloses a semiconductor device, comprising:
an N-type semiconductor substrate 64;
an epitaxial layer 66/68/70 (fig. 3A and par [0063] - epitaxial), disposed on the semiconductor substrate;
a trench structure (fig. 3B), disposed at the epitaxial layer, wherein the trench structure comprises: a plurality of first trenches (74a/b) that extend in a first direction Y parallel to a plane on which the semiconductor substrate is located and are arranged at intervals in a second direction X parallel to the plane on which the semiconductor substrate is located (par [0065]); and
a gate 82a that is filled and disposed in the trench structure and is spaced apart by a gate dielectric layer 80a;
an interlayer dielectric layer 86 that is disposed on the gate and covers the gate, wherein the interlayer dielectric layer comprises a contact hole 88 that extends in the second direction and exposes a partial region of the epitaxial layer, wherein a projection of the contact hole in a third direction perpendicular to the plane on which the semiconductor substrate is located does not overlap the gate, and wherein the first direction, the second direction, and the third direction are set in a cross manner;
a source 50 that is disposed at the interlayer dielectric layer and is in contact, through the contact hole, with the epitaxial layer exposed by the contact hole; and
a drain 52 that is disposed on a side of the semiconductor substrate and away from the epitaxial layer.
Saggio does not disclose a second trench that extends in the second direction, wherein the second trench and each of the plurality of first trenches are disposed in a cross manner and communicate with each other.
PNG
media_image3.png
395
502
media_image3.png
Greyscale
However, FIG. 1 of REN schematically shows a trench-gate MOSFET cell 000 comprising a trench structure, wherein the trench structure comprises: a plurality of first trenches (note fig. 1 is for cell 000 and there are more than one cell formed on the substrate) that extend in a first direction Y parallel to a plane on which a semiconductor substrate is located and are arranged at intervals in a second direction; and a second trench that extends in the second direction, wherein the second trench and each of the plurality of first trenches are disposed in a cross manner and communicate with each other.
Note the trench structure of REN has benefit of more gate to channel surface for more current flow to create a more powerful trench-gate power MOSFET.
As such it would have been obvious to form a device of Saggio further comprising a second trench that extends in the second direction, wherein the second trench and each of the plurality of first trenches are disposed in a cross manner and communicate with each other such as taught by REN in order to produce more gate to channel surface for more current flow to create a more powerful trench-gate power MOSFET.
Saggio and REN do not disclose a power conversion circuit, comprising: a circuit board; and one or more semiconductor devices connected to the circuit board.
PNG
media_image5.png
501
718
media_image5.png
Greyscale
However, fig. 1 of Akama discloses of a power conversion circuit, comprising: a circuit board (that which all the elements are connected on is a board); and one or more semiconductor devices 3a-3i connected to the circuit board to form a rotary machine driving apparatus 1 that is supplied with driving power voltage VB from a battery (not shown) for vehicle driving power.
As such it would have been obvious to form one of more semiconductor devices of Saggio and REN connected a circuit board forming a power conversion circuit to form a rotary machine driving apparatus for vehicle driving power
Regarding claim 20, the resulting structure of Saggio and REN and Akama discloses a vehicle, comprising the power conversion circuit according to claim 19, wherein the power conversion circuit is configured to convert an alternating current and/or a direct current and output a direct current (fig. 1 is a rotary machine which used to provide DC power from an AC power source.)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
Prosecution Insights