DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed July 28, 2026, have been fully considered, in view of the amendments to the claims, and are persuasive regarding independent claims 8 and 20 and the claims respectively dependent thereto.
Applicant's arguments regarding amended independent claim 1 have been fully considered, but are not persuasive in view of a rejection relying upon the combination of US Publication 2022/0076890 to Cho et al. (hereinafter Cho) in view of FIG. 11-12 of US Publication 2010/0039784 to Hayashi, as set forth below, and in view of a rejection relying upon the combination of Cho with US Publication 2006/0050491 to Hayashi et al. (hereinafter ‘491), as set forth below.
In response to applicant's arguments against the references individually, e.g., “Cho fails to disclose or fairly suggest a semiconductor device mounted on the same wiring board… Cho does not discuss that the two stacked capacitors are used as a decoupling capacitor structure” (Remarks 15), “Hayashi fails to disclose or fairly suggest a first capacitor and a second capacitor stacked to each other” (Remarks 15), and “Hayashi '491 does not disclose two capacitors stacked on one another” (Remarks 18), one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Accordingly, to the extent applicant’s arguments apply to the grounds of rejection set forth below, applicant’s arguments have been fully considered but are not persuasive.
Drawings
Drawing sheets were received July 28, 2026, and the objection to the drawings is withdrawn.
Specification
The objection to the disclosure is withdrawn.
Claim Rejections - 35 USC § 112
The rejection of claims 20-22 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, is withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-4, 7, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Hayashi.
Claim 1
Cho (FIG. 1-10) discloses a circuit board comprising:
a wiring board (210); and
a first capacitor (100) and a second capacitor (101) that are stacked to each other on the wiring board (210);
wherein the first capacitor (100) is provided between the second capacitor (101) and the wiring board (210),
wherein a second capacitance of the second capacitor (101) is larger than a first capacitance of the first capacitor (100; FIG. 7: same material, same number of layers, same size except 101 is longer and has a greater area of electrode overlap and therefore a higher capacitance),
wherein the first capacitor (100) has a first terminal (131) and a second terminal (132), and
wherein the second capacitor (101) has a first terminal (131’) and a second terminal (132’), as recited in claim 1.
Cho does not expressly disclose a semiconductor device that is mounted on the wiring board, wherein the wiring board has a first power supply wiring connected to a first terminal of the semiconductor device and a second power supply wiring connected to a second terminal of the semiconductor device, wherein the first terminal of the first capacitor and the first terminal of the second capacitor are electrically connected to the first power supply wiring, and the second terminal of the first capacitor and the second terminal of the second capacitor are electrically connected to the second power supply wiring, as recited in claim 1.
Hayashi (FIG. 11) teaches a semiconductor device (602) mounted on a wiring board (601), wherein the wiring board (601) has a first power supply wiring (610) connected to a first terminal (606) of the semiconductor device (601) and a second power supply wiring (611) connected to a second terminal (605) of the semiconductor device (601), wherein a first capacitor (613) has a first terminal and a second terminal, wherein the first terminal of the first capacitor (613) is electrically connected to the first power supply wiring (610), and the second terminal of the first capacitor (613) is electrically connected to the second power supply wiring (611).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Cho with Hayashi to incorporate stacked capacitors as taught by Cho in the structure taught by Hayashi to replace a singular capacitor 613 with the stacked capacitors of Cho and thereby have a semiconductor device that is mounted on the wiring board, wherein the wiring board has a first power supply wiring connected to a first terminal of the semiconductor device and a second power supply wiring connected to a second terminal of the semiconductor device, as taught by Hayashi, wherein the first terminal of the first capacitor and the first terminal of the second capacitor electrically connected to the first power supply wiring (the stacked capacitors of Cho), and the second terminal of the first capacitor and the second terminal of the second capacitor are electrically connected to the second power supply wiring (the stacked capacitors of Cho), as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for high capacitance without increased mounting area and for avoiding acoustic noise (Cho paragraph 10) when used in the arrangement of Hayashi to reduce common mode noise.
Claim 3
Cho with Hayashi teaches the circuit board according to claim 1, as shown above.
Hayashi does not expressly disclose wherein the first capacitor and the second capacitor are arranged from the semiconductor device within 50 millimeters (mm), as recited in claim 3.
Such an arrangement, however, would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention as matter of routine optimization, given that Hayashi teaches locating the capacitors adjacent to the component, thereby reducing impedance, voltage drop, and noise.
Additionally, where the only difference between the prior art and the claim is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device. See MPEP 2144.04 citing In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Claim 4
Cho with Hayashi teaches the circuit board according to claim 1, wherein the semiconductor device (Hayashi 602) is mounted on a mounting surface on which the first capacitor (Hayashi 613 in view of Cho) is mounted (Hayashi FIG. 11).
Claim 7
Cho with Hayashi teaches the circuit board according to claim 1, wherein a center of the first capacitor (Cho 100) and a center of the second capacitor (101) are arranged on a straight line in a stacking direction of the first capacitor (100) and the second capacitor (101; Cho FIG. 10).
Claim 19
Cho with Hayashi teaches an electronic device comprising:
the circuit board according to claim 1 (as shown above); and
an electrical apparatus (Hayashi paragraph 34-36: power supply; see also Cho paragraph 3-4) that is connected to the circuit board.
Claims 1, 3, 5-7, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of ‘491.
Claim 1
Cho (FIG. 1-10) discloses a circuit board comprising:
a wiring board (210); and
a first capacitor (100) and a second capacitor (101) that are stacked to each other on the wiring board (210);
wherein the first capacitor (100) is provided between the second capacitor (101) and the wiring board (210),
wherein a second capacitance of the second capacitor (101) is larger than a first capacitance of the first capacitor (100; FIG. 7: same material, same number of layers, same size except 101 is longer and has a greater area of electrode overlap and therefore a higher capacitance),
wherein the first capacitor (100) has a first terminal (131) and a second terminal (132), and
wherein the second capacitor (101) has a first terminal (131’) and a second terminal (132’), as recited in claim 1.
Cho does not expressly disclose a semiconductor device that is mounted on the wiring board, wherein the wiring board has a first power supply wiring connected to a first terminal of the semiconductor device and a second power supply wiring connected to a second terminal of the semiconductor device, wherein the first terminal of the first capacitor and the first terminal of the second capacitor are electrically connected to the first power supply wiring, and the second terminal of the first capacitor and the second terminal of the second capacitor are electrically connected to the second power supply wiring, as recited in claim 1.
‘491 (FIG. 1, paragraph 39) teaches a semiconductor device (201) mounted on a wiring board (paragraph 39), wherein the wiring board has a first power supply wiring (206, 210) connected to a first terminal (202) of the semiconductor device (201) and a second power supply wiring (213, paragraph 39: “a ground via hole 213 that constitutes the shortest path for a current through the bypass capacitor 212 to go back to the ground terminal 203”) connected to a second terminal (203) of the semiconductor device (201), wherein a first capacitor (212) has a first terminal and a second terminal, wherein the first terminal of the first capacitor (212) is electrically connected to the first power supply wiring (206, 210), and the second terminal of the first capacitor (212) is electrically connected to the second power supply wiring (213).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Cho with ‘491 to incorporate stacked capacitors as taught by Cho in the structure taught by ‘491 to replace the singular bypass capacitor 212 of ‘491 with the stacked capacitors of Cho and thereby have a semiconductor device that is mounted on the wiring board, wherein the wiring board has a first power supply wiring connected to a first terminal of the semiconductor device and a second power supply wiring connected to a second terminal of the semiconductor device, as taught by ‘491, wherein the first terminal of the first capacitor and the first terminal of the second capacitor electrically connected to the first power supply wiring (the stacked capacitors of Cho), and the second terminal of the first capacitor and the second terminal of the second capacitor are electrically connected to the second power supply wiring (the stacked capacitors of Cho), as one having ordinary skill in the art would have been motivated to do this with a reasonable expectation of success because such a combination and/or modification allows for high capacitance without increased mounting area and for avoiding acoustic noise (Cho paragraph 10) when used in the arrangement of ‘491 to have a more stable power supply (‘491 paragraph 46).
Claim 3
Cho with ‘491 teaches the circuit board according to claim 1, wherein the first capacitor (‘491 212 in view of Cho 100) and the second capacitor (‘491 212 in view of Cho 101) are arranged from the semiconductor device (‘491 201) within 50 millimeters (mm)(‘491 FIG. 1, 4, paragraph 45, 50).
Additionally, where the only difference between the prior art and the claim is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device. See MPEP 2144.04 citing In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Claim 5
Cho with ‘491 teaches the circuit board according to claim 1, wherein the semiconductor device (‘491 201) is mounted on a second mounting surface opposite to a first mounting surface on which the first capacitor (‘491 212 in view of Cho 100) is mounted on the wiring board (‘491 FIG. 1, paragraph 39, “Although the bypass capacitor 212 is actually disposed on the back face of the second surface-layer conductor 209, the bypass capacitor 212 is disposed on the front face of the second surface-layer conductor 209 in FIG. 1 for the sake of simplifying the illustration”).
Claim 6
Cho with ‘491 teaches the circuit board according to claim 1, wherein the first capacitor (‘491 212 in view of Cho 100) and the second capacitor (‘491 212 in view of Cho 101) are arranged at a position overlapping the semiconductor device (‘491 201) in a direction perpendicular to a first mounting surface on which the first capacitor (‘491 212 in view of Cho 100) is mounted on the wiring board (‘491 FIG. 1, 6, and 8).
Claim 7
Cho with ‘491 teaches the circuit board according to claim 1, wherein a center of the first capacitor (Cho 100) and a center of the second capacitor (101) are arranged on a straight line in a stacking direction of the first capacitor (100) and the second capacitor (101; Cho FIG. 10).
Claim 19
Cho with ‘491 teaches an electronic device comprising:
the circuit board according to claim 1 (as shown above); and
an electrical apparatus (‘491 paragraph 35: power supply; see also Cho paragraph 3-4) that is connected to the circuit board.
Allowable Subject Matter
Claims 8-18, 20-22, and 24 are allowed.
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN MILAKOVICH whose telephone number is (571)270-3087. The examiner can normally be reached Monday - Friday 9:00 AM - 5:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN MILAKOVICH/Primary Examiner, Art Unit 2847
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