DETAILED ACTION
This office action is in response to the amendment filed 02/04/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-11, and 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iida et al. (“Iida”, US 6,137,700) in view of Zeng et al. (“Zeng”, CN113972827B).
Re claim 1, Iida teaches a power supply unit [Fig 6] for an information handling system, the power supply unit comprising: a voltage rectifier/voltage doubler stage [2] configured to receive an alternating current input [from Vin] and to provide a direct current output [Vdc]; and a bulk capacitor stage [C11, C12] coupled between the direct current output, wherein when an input voltage of the alternating current input is above a threshold voltage [Command value], the voltage regulator/voltage double stage is configured as a full-wave synchronous voltage rectifier, and when the input voltage is below the threshold voltage, the voltage rectifier/voltage doubler stage is configured as a full-wave synchronous voltage doubler [Col 12, ln 44-50]; wherein the voltage rectifier/voltage doubler stage includes: a first element [2a, see below] having a first contact type coupled to a positive side of the alternating current input, and having a second contact type couple to a positive side of the direct current output; a second element [2b] having the first contact type coupled to a negative side of the direct current output, and having the second contact type couple to the positive side of the alternating current input; a third element [2c] having the first contact type coupled to the negative side of the alternating current input, and having the second contact type couple to the positive side of the direct current output; and a fourth element [2d] having the first contact type coupled to the negative side of the direct current output, and having the second contact type coupled to the negative side of the alternating current input, but does not teach the first element, the second element, the third element, and the fourth element being MOSFETs.
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Zeng teaches a device [Fig 1] having a first MOSFET [Q1], a second MOSFET [Q2], a third MOSFET [Q3], and a fourth MOSFET [Q4, as described in paragraph [n0106]]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Iida to include the features of Zeng because MOSFETs excel in high-current, low-voltage applications which leads to reduction of power losses, thus improving the utility of the device, which increases efficiency.
Re claim 3, Iida teaches wherein, when the input voltage of the alternating current input is above the threshold voltage, the first element, the second element, the third element, and the fourth element all conduct current during a single cycle of the alternating current input [124 is open causing all diodes to conduct, Col 12, ln 44-50]; but does not teach the first element, the second element, the third element, and the fourth element being MOSFETs.
Zeng teaches a device [Fig 1] having a first MOSFET [Q1], a second MOSFET [Q2], a third MOSFET [Q3], and a fourth MOSFET [Q4, as described in paragraph [n0106]]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Iida to include the features of Zeng because MOSFETs excel in high-current, low-voltage applications which leads to reduction of power losses, thus improving the utility of the device, which increases efficiency.
Re claim 4, Iida teaches wherein, when the input voltage of the alternating current input is below the threshold voltage, the first element and the second element both conduct current during a single cycle of the alternating current input, and neither the third element nor the fourth element conduct current during the single cycle [S1 is closed causing voltage doubler rectification, Col 11, ln 55-59], but does not teach the first element, the second element, the third element, and the fourth element being MOSFETs.
Zeng teaches a device [Fig 1] having a first MOSFET [Q1], a second MOSFET [Q2], a third MOSFET [Q3], and a fourth MOSFET [Q4, as described in paragraph [n0106]]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Iida to include the features of Zeng because MOSFETs excel in high-current, low-voltage applications which leads to reduction of power losses, thus improving the utility of the device, which increases efficiency.
Re claim 5, Iida teaches wherein the bulk capacitor stage includes a first capacitor [C11] and a second capacitor [C12].
Re claim 6, Iida teaches wherein a first terminal of the first capacitor is coupled to a positive side of the direct current output, a second terminal of the first capacitor is coupled to a first terminal of the second capacitor, and a second terminal of the second capacitor is coupled to a negative side of the direct current output [as shown in Fig 6].
Re claim 7, Iida teaches a switch [S1] having a first terminal coupled to a negative side of the alternating current input and a second terminal coupled to the second terminal of the first capacitor and to the second terminal of the second capacitor [as shown in Fig 6].
Re claim 8, Iida teaches when the input voltage of the alternating current input is above the threshold voltage, the switch is in an open state, and, when the input voltage of the alternating current input is below the threshold voltage, the switch is in a closed state [Col 12, ln 44-50].
Re claim 9, Iida teaches a controller [13] configured to detect the input voltage of the alternating current input [using 13a, Col 12, ln 35-36].
Re claim 10, Iida teaches wherein the controller is further configured to set the switch to the open state when the input voltage of the alternating current input is above the threshold voltage, and to set the switch to the closed state when the input voltage of the alternating current input is below the threshold voltage [Col 12, ln 44-50].
Re claim 11, Iida teaches a method, comprising: receiving, by a voltage rectifier/voltage doubler stage [2] of a power supply unit [Fig 6], an alternating current input [at Vin]; providing, by the voltage rectifier/voltage doubler stage, a direct current output [Vdc]; coupling a bulk capacitor stage [C11, C12] between the direct current output; configuring the voltage regulator/voltage double stage as a full-wave synchronous voltage rectifier when an input voltage of the alternating current input is above a threshold voltage [Command value]; and configuring the voltage regulator/voltage double stage is configured as a full-wave synchronous voltage doubler when the input voltage is below the threshold voltage [Col 12, ln 44-50]; providing, in the voltage rectifier/voltage doubler, stage, a first element [2a] having a first contact type coupled to a positive side of the alternating current input, and having a second contact type couple to a positive side of the direct current output; providing, in the voltage rectifier/voltage doubler, stage, a second element [2b] having the first contact type coupled to a negative side of the direct current output, and having the second contact type couple to the positive side of the alternating current input; providing, in the voltage rectifier/voltage doubler, stage, a third element [2c] having the first contact type coupled to the negative side of the alternating current input, and having the second contact type couple to the positive side of the direct current output; and providing, in the voltage rectifier/voltage doubler, stage, a fourth element [2d] having the first contact type coupled to the negative side of the direct current output, and having the second contact type couple to the negative side of the alternating current input [as shown in Fig 6], but does not teach the first element, the second element, the third element, and the fourth element being MOSFETs.
Zeng teaches a device [Fig 1] having a first MOSFET [Q1], a second MOSFET [Q2], a third MOSFET [Q3], and a fourth MOSFET [Q4, as described in paragraph [n0106]]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Iida to include the features of Zeng because MOSFETs excel in high-current, low-voltage applications which leads to reduction of power losses, thus improving the utility of the device, which increases efficiency.
Re claim 13, Iida teaches when the input voltage of the alternating current input is above the threshold voltage, the first element, the second element, the third element, and the fourth element all conduct current during a single cycle of the alternating current input [124 is open causing all diodes to conduct, Col 12, ln 44-50]; but does not teach the first element, the second element, the third element, and the fourth element being MOSFETs.
Zeng teaches a device [Fig 1] having a first MOSFET [Q1], a second MOSFET [Q2], a third MOSFET [Q3], and a fourth MOSFET [Q4, as described in paragraph [n0106]]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Iida to include the features of Zeng because MOSFETs excel in high-current, low-voltage applications which leads to reduction of power losses, thus improving the utility of the device, which increases efficiency.
Re claim 14, Iida teaches when the input voltage of the alternating current input is below the threshold voltage, the first element and the second element both conduct current during a single cycle of the alternating current input, and neither the third element nor the fourth element conduct current during the single cycle [S1 is closed causing voltage doubler rectification, Col 11, ln 55-59], but does not teach the first element, the second element, the third element, and the fourth element being MOSFETs.
Zeng teaches a device [Fig 1] having a first MOSFET [Q1], a second MOSFET [Q2], a third MOSFET [Q3], and a fourth MOSFET [Q4, as described in paragraph [n0106]]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Iida to include the features of Zeng because MOSFETs excel in high-current, low-voltage applications which leads to reduction of power losses, thus improving the utility of the device, which increases efficiency.
Re claim 15, Iida teaches providing, in the bulk capacitor stage, a first capacitor [C11] and a second capacitor [C12].
Re claim 16, Iida teaches wherein a first terminal of the first capacitor [C11] is coupled to a positive side of the direct current output, a second terminal of the first capacitor is coupled to a first terminal of the second capacitor, and a second terminal of the second capacitor [C12] is coupled to a negative side of the direct current output [as shown in Fig 6].
Re claim 17, Iida teaches providing, in the power supply unit, a switch [S1] having a first terminal coupled to a negative side of the alternating current input and a second terminal coupled to the second terminal of the first capacitor [C11] and to the second terminal of the second capacitor [C12, as shown in Fig 6].
Re claim 18, Iida teaches wherein, when the input voltage of the alternating current input is above the threshold voltage, the switch is in an open state, and, when the input voltage of the alternating current input is below the threshold voltage, the switch is in a closed state [Col 12, ln 44-50].
Re claim 19, Iida teaches providing, in the power supply unit, a controller [13]; detecting, by the controller, the input voltage of the alternating current input; setting, by the controller, the switch to the open state when the input voltage of the alternating current input is above the threshold voltage; and setting, by the controller, the switch to the closed state when the input voltage of the alternating current input is below the threshold voltage [using 13a, Col 12, ln 35-36].
Re claim 20, Iida teaches a power supply unit [Fig 6] for an information handling system, the power supply unit comprising: a voltage rectifier/voltage doubler stage [2] configured to receive an alternating current input [at Vin] and to provide a direct current output [Vdc], the voltage rectifier/voltage doubler stage including: a first element [2a] having a first contact type coupled to a positive side of the alternating current input, and having a second contact type couple to a positive side of the direct current output; a second element [2b] having the first contact type coupled to a negative side of the direct current output, and having the second contact type coupled to the positive side of the alternating current input; a third element [2c] having the first contact type coupled to the negative side of the alternating current input, and having the second contact type coupled to the positive side of the direct current output; and a fourth element [2d] having the first contact type coupled to the negative side of the direct current output, and having the second contact type coupled to the negative side of the alternating current input; a bulk capacitor stage [C11, C12] coupled between the direct current output, the bulk capacitor including a first capacitor [C11] and a second capacitor [C12], wherein a first terminal of the first capacitor is coupled to the positive side of the direct current output, a second terminal of the first capacitor is coupled to a first terminal of the second capacitor, and a second terminal of the second capacitor is coupled to the negative side of the direct current output [as shown in Fig 6]; and a switch [S1] having a first terminal coupled to a negative side of the alternating current input and a second terminal coupled to the second terminal of the first capacitor and to the second terminal of the second capacitor [as shown in Fig 6]; wherein when an input voltage of the alternating current input is above a threshold voltage, the voltage regulator/voltage double stage is configured as a full-wave synchronous voltage rectifier, and when the input voltage is below the threshold voltage, the voltage rectifier/voltage doubler stage is configured as a full-wave synchronous voltage doubler [Col 12, ln 44-50], but does not teach the first element, the second element, the third element, and the fourth element being MOSFETs.
Zeng teaches a device [Fig 1] having a first MOSFET [Q1], a second MOSFET [Q2], a third MOSFET [Q3], and a fourth MOSFET [Q4, as described in paragraph [n0106]]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Iida to include the features of Zeng because MOSFETs excel in high-current, low-voltage applications which leads to reduction of power losses, thus improving the utility of the device, which increases efficiency.
Response to Arguments
Applicant’s argument with respect to claims 1, 3-11, and 13-20 have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LaKaisha Jackson/
Examiner, Art Unit 2838