DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The instant application with Application Number 18/642,827 filed on 04/27/2024 is presented for examination. Claims 1-11 are pending.
Information Disclosure Statment
The Information Disclosure Statement dated 04/23/2024 is acknowledged and the cited references have been considered in this examination.
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Densham et al. (US 2014/0084871) (Hereinafter, Densham) in view of Tagaya et al. (US 2014/0015483).
With respect to claims 1, 9 and 11, Densham discloses a cell balance switch circuit (Fig. 3-5; Para. # 0050: system 500 can charge/balance cells in multiple battery), comprising: (n+1) electrodes, configured to be each connected with a common node of adjacent two battery cells among n battery cells connected in series (Fig. 3, 210; para. # 0053: plurality of cells 210_1-210_N and distributes the energy to the cells 210_1-210_N. The cells 210_1-210_N are balanced relative to one another based on the energy from the cells 210_1-210_N), a cell string comprising the n battery cells; (n+1) conductive wires, respectively connected with the electrodes; and n cell balance switches (Fig. 3, 312_1-312_N),
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a cell string comprising the n battery cells; (n+1) conductive wires, respectively connected with the electrodes; and n cell balance switches (Fig. 3, 312_1-312_N), configured to be connected between adjacent two conductive wires among the conductive wires, wherein: each of the cell balance switches (Fig. 3, switch controller 340 and switches 312; Para. # 0031) comprises: a first transistor, connected between adjacent conductive wires of the conductive wires (Para. # 0023, and 0055:Fig. 3, transistors 312) ; a bias wire, connected with a gate of the first transistor (Fig. 3, wires connected to control switch 340 generating control signals).
Densham does not expressly disclose a suppression circuit comprises a switch configured to temporarily connect the bias wire and the conductive wire in response to a voltage change.
Tagaya, on the other hand, discloses a suppression circuit comprises a switch configured to temporarily connect the bias wire and the conductive wire in response to a voltage change (Para. # 123: electric power used to balance the voltages of the respective cells can be saved, which means effectively suppression of dispersion of voltages).
DENSHAM and Tagaya are analogous art because they are from the same field of endeavor namely battery system and method for balancing battery cells and battery management.
It would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to have added a suppression circuit to the balancing circuit of Densham in view of Tagaya for the benefit of reducing dispersion of voltages to avoid voltage inequalities between cells (Para. # 124 and 127).
With respect to claim 2, the combined references of Densham and Tagaya disclose the cell balance switch circuit as described above, further Densham discloses wherein the suppression circuit comprises a second transistor having a source and a drain respectively connected with the conductive wire and the bias wire associated with the suppression circuit (Para. # 0023: sw 108 has multiple transistor, the switch 108 is an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET).
With respect to claim 3, the combined references of Densham and Tagaya disclose the cell balance switch circuit as described above, further Densham discloses a delay circuit connected between the conductive wire associated with the suppression circuit and a gate of the second transistor (Fig. 3, gate of transistors 312).
With respect to claims 4 and 10, the combined references of Densham and Tagaya disclose the cell balance switch circuit as described above, further Densham discloses wherein the suppression circuit further comprises: a resistor, connected between a gate of the second transistor and the conductive wire; and a capacitor, connected between the gate and the drain of the second transistor (Para. # 0016/0019: a resistor 114, is coupled in series to the primary winding 104, such that a voltage V.sub.114 across the resistor 114; further the switch circuit and contains multiple resisters across the balancing circuit to control the voltages).
With respect to claim 5, the combined references of Densham and Tagaya disclose the cell balance switch circuit as described above, further Densham discloses wherein the cell balance switch further comprises a diode connected in a reverse direction between the bias wire and the conductive wire (Para. # 0017: he diode 112 is reverse biased (cut off), and the secondary winding 106).
With respect to claim 6, the combined references of Densham and Tagaya disclose the cell balance switch circuit as described above, further Densham discloses wherein a conductivity type of the second transistor is same as a conductivity type of the first transistor of the cell balance switch (Fig. 3, transistors of 312_1 to 312_N).
With respect to claim 7, the combined references of Densham and Tagaya disclose the cell balance switch circuit as described above, further Densham discloses wherein at least some of the first transistors of the cell balance switches have a p-channel type (Para. # 0024: a switch (not shown in FIG. 1A) that is a p-channel MOSFET (PMOSFET)).
With respect to claim 8, the combined references of Densham and Tagaya disclose the cell balance switch circuit as described above, further Densham discloses wherein at least some of the first transistors of the cell balance switches have an n-channel type (Para. # 0023: SW 108 is an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YALKEW FANTU whose telephone number is (571)272-8928. The examiner can normally be reached Monday-Friday 7:00AM-4:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW A DUNN can be reached at 571-272-2312. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YALKEW FANTU/Primary Examiner, Art Unit 2859
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