Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18642841 filed on 04/23/2024.
Information Disclosure Statement
The information disclosure statement filed on 04/23/2024 has been considered.
Specifications Objections
The Specification filed on 04/23/2024 is objected to because of the following formalities: where it recites in paragraph [0062] the opening 21 should be 210. Appropriate correction is required.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a) -(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant elected without traverse of claims 1, 2, 4-12, 15 & 16 (Group I, species IA) in a telephonic Interview dated 05/21/2026. The restriction requirement is as follows:
Restriction to one of the following inventions is required under 35 U.S.C. 121:
Claim 1-16 directed to an array substrate classified in [H10D86/441].
Claim 17-19, directed to a method for forming an array substrate classified in [H10D86/0231].
Inventions I and II are related as process of making and product made. The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another materially different product or (2) that the product as claimed can be made by another materially different process (MPEP § 806.05(f)).
In this case the product as claimed can be made by another materially different process such as selectively depositing the insulative material layer instead of patterning insulation layer to form an opening in the first area and second area.
Restriction for examination purposes as indicated is proper because all these inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restrictions were not required because one or more of the following reasons apply:
The inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search queries and the inventions have acquired a separate status in the art in view of their different classification.
Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention or a grouping of patentably indistinct invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention.
This application also contains claims directed to the following patentably distinct species.
If applicants choose to elect Group I, an election of species is required to choose as follows:
Species IA: Figures 4 & 5 directed to an array substrate in which plurality of first areas are adjacent to each other to form a step shape but it doesn’t disclose a second conductive part, arranged at a side of the insulating layer facing the substrate, wherein the second conductive part and the first conductive part are overlapped to form an overlapped area.
Species IB: Figures 6 & 8 directed to an array substrate in which plurality of first areas are spaced but it doesn’t disclose a second conductive part, arranged at a side of the insulating layer facing the substrate, wherein the second conductive part and the first conductive part are overlapped to form an overlapped area.
Species IC: Figures 9 & 10 directed to an array substrate in which a third opening and the first area are arranged around the third opening and adjacent to the third opening, but it doesn’t disclose plurality of first areas are spaced.
Species ID: Figures 11 & 12 directed to an array substrate in which a third opening and plurality of first areas are arranged around the third opening and adjacent to the third opening, but it doesn’t disclose plurality of first areas are spaced.
If applicants choose to elect Group II, an election of species is additionally required to choose as follows:
Species IIA: Figures 17 & 18 directed to a method for forming an array substrate, in which the first mask plate is irradiated from the side of the first mask plate away from the insulating material layer to form the opening at a position corresponding to the first via (610) and form the first area at a position corresponding to the first light-shielding area, and form the second area at a position corresponding to the second light-shielding area.
Species IIB: Figure 20 directed to a method for forming an array substrate, in which the second mask plate comprises a second via, a third light-shielding area and a fourth light-shielding area, and the third light-shielding area comprises a plurality of spaced slits.
The species are independent or distinct because applicant have not shown an embodiment which combines all the species; therefore, examiner indicates that by applicants’ disclosure, each species is mutually exclusive. In addition, these species are not obvious variants of each other based on the current record due to the mutually exclusive characteristics indicated above.
Applicant is required under 35 U.S.C. 121 to elect a single disclosed species, or a single grouping of patentably indistinct species, for prosecution on the merits to which the claims shall be restricted if no generic claim is finally held to be allowable. Currently, the independent claims appear to be generic.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
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Claims 1, 2, 4-6, 15 & 16 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kim et al. (US 2021/0367000 A1).
Regarding Independent claim 1, Kim et al. teach an array substrate, comprising:
a substrate (fig. 14, element SUB [0078]);
an insulating layer (fig. 14, elements IL1 & IL2 [0102]), arranged at a side of the substrate (fig. 14),
wherein the insulating layer is provided with an opening (fig. 14, element HO
defined hole in the hole area of element HA, [0068] [0045]),
the insulating layer comprises a first area (see annotated figure above) and a second area (see annotated figure above),
a thickness of the first area is less than a thickness of the second area (see annotated figure above, thickness of each down steps of IL1 & IL2 is less than the thickness of full height portion of top level of IL1 & IL2),
and the first area is arranged around at least a part of the opening (fig. 14, the bottom portion of step structure is located at the hole area element HA, containing a hole element HO);
and a first conductive part (fig. 14, element LN [0183]), arranged at a side of the insulating layer away from the substrate (fig. 14),
wherein an orthographic projection of the first conductive part on the substrate and an orthographic projection of the first area on the substrate are at least partially overlapped (fig. 14).
Regarding claim 2, Kim et al. teach the array substrate,
wherein a number of the first area is plural (see annotated figure above), and a plurality of first areas are arranged side by side in a direction away from the opening (see annotated figure above).
Regarding claim 4, Kim et al. teach the array substrate,
wherein thicknesses of the plurality of the first areas are gradually decreased in a direction of approaching the opening (see annotated figure above, thickness of the plurality of the first areas are gradually decreased in a direction of approaching the hole area HA [0085]).
Regarding claim 5, Kim et al. teach the array substrate,
wherein the plurality of first areas are adjacent to each other to form a step-shaped surface of the insulating layer away from the substrate (see annotated figure above);
or the plurality of first areas are spaced.
Regarding claim 6, Kim et al. teach the array substrate,
wherein the opening (fig. 14, hole area, element HA [0045]) comprise a first opening (fig. 14, element HO [0068]),
the first opening and the first conductive part are spaced (fig. 14, element HO and element LN are spaced) and at least a part of the first conductive part is arranged around the first opening (fig. 14).
Regarding independent claim 15, Kim et al. teach a display panel, comprising
an array substrate (plurality of pixels, element PX [0085]),
wherein the array substrate comprises:
a substrate (fig. 14, element SUB [0078]);
an insulating layer (fig. 14, elements IL1 & IL2 [0102]), arranged at a side of the substrate (fig. 14),
wherein the insulating layer is provided with an opening (fig 14, element HO
defined hole in the hole area of element HA, [0068] [0045]),
the insulating layer comprises a first area (see annotated figure above) and a second area (see annotated figure above),
a thickness of the first area is less than a thickness of the second area (see annotated figure above, thickness of each down steps of IL1 & IL2 is less than the thickness of full height portion of top level of IL1 & IL2),
and a first conductive part (fig. 14, element LN [0183]), arranged at a side of the insulating layer away from the substrate (fig. 14),
wherein an orthographic projection of the first conductive part on the substrate and an orthographic projection of the first area on the substrate are at least partially overlapped (fig. 14).
Regarding claim 16, Kim et al. teach a display device,
comprising the display panel (fig. 2, element DP, [0006]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2021/0367000 A1) in view of Zhang et al. (2022/0320231 A1).
Regarding claim 7, Kim et al. teach all the limitations as discussed above.
Kim et al. do not explicitly teach the first conductive part comprises a first segment and a second segment connected in sequence, the first segment is arranged around the first opening, and the second segment is connected to a terminal of the first segment, wherein the second segment is extended and formed in a direction away from the first opening, an orthographic projection of the first conductive part on the substrate and an orthographic projection of the first area on the substrate are at least partially overlapped.
However, Zhang et al. is a pertinent art which teaches first conductive part comprises
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a first segment (see annotated figure above of Zhang, the signal line 2303 partially disposes around the first opening 201A within the first opening peripheral region 203A comprises a first segment which is curved portion [0060] [0054])
and a second segment (see annotated figure above of Zhang, the signal line 2303 partially dispose around the first opening 201A within the first opening peripheral region 203A and comprises a second segment which is straight line portion [0060] [0054) connected in sequence (see annotated figure above of Zhang),
the first segment is arranged around the first opening (see annotated figure above of Zhang, the signal line 2303 comprise first segment which is curved portion arranged around the first opening 201A [0054] [0060]),
and the second segment is connected to a terminal (fig. 2B of Zhang discloses connection to VDD terminal [0064]) of the first segment (see annotated figure above of Zhang),
wherein the second segment is extended and formed in a direction away from the first opening (see annotated figure above of Zhang, the signal line 2303 comprises a second segment which is straight line portion connected to a terminal of the first segment and direction away from the first opening 201A towards the first display region 2011 [0054] [0059] [0060] [0180]).
an orthographic projection of the first conductive part on the substrate and an orthographic projection of the first area on the substrate are at least partially overlapped (see annotated figure above of Zhang).
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filling date of the claimed invention to modify the array substrate of Kim et al. as taught by Zhang et al. with the motivation to simplify signal routing path [0004] [0005].
Regarding claim 8, Kim et al. as modified by Zhang et al. teach the array substrate, wherein
the first segment (see annotated figure above of Zhang, the signal line 2303 partially disposes around the first opening 201A within the first opening peripheral region 203A, and comprises a first segment which is curved portion [0054] [0059]) comprises
a first sub-segment (see annotated figure above of Zhang, the signal line 2301 partially dispose around the first opening 201A comprises a first sub segment which is curved portion)
and a second sub-segment (see annotated figure above of Zhang, the signal line 2301 partially dispose around the first opening 201A and comprises a second sub segment which is straight line portion)
the first sub-segment is located at a side of the first opening (see annotated figure above of Zhang, the signal line 2301 comprises a first sub segment which is curved portion partially dispose at a side of the first opening) in a first direction (figs. 2A-2C of Zhang),
and the first sub-segment is extended and formed in a second direction (see annotated figure above of Zhang, the signal line 2301 partially dispose around the first opening 201A comprises a first sub segment which is curved portion is extended and formed in a second direction)
the second sub-segment is located at a side of the first opening in the second direction (see annotated figure above of Zhang, the signal line 2301 partially dispose around the first opening 201A and comprises a second sub segment which is straight line portion in the second direction),
and the second sub-segment is extended and formed in the first direction (see annotated figure above of Zhang),
the second segment (see annotated figure above of Zhang, the signal line 2303 partially dispose around the first opening 201A and comprises a second segment which is straight line portion [0060] [0054]) is connected to a terminal (figs. 2A-2C of Zhang, disclose connection to VDD terminal [0064]) of the second sub-segment away from the first segment (see annotated figure above),
the second segment is extended and formed in the second direction away from the first opening (see annotated figure above of Zhang, the signal line 2303 partially dispose around the first opening 201A and comprises a second segment which is straight line portion extended and formed in the second direction away from the opening).
Regarding claim 9, Kim et al. as modified by Zhang et al. teach the array substrate, wherein
the opening further comprises a second opening (fig. 5A of Zhang is an enlarged schematic diagram of portion C of fig. 2C [0097], element VH12 is via hole through first portion element 2301A of the same first signal line 2301 [0099])
an orthographic projection of the second opening on the substrate and an orthographic projection of the second segment on the substrate are at least partially overlapped (fig. 5A of Zhang),
the minimum distance between the first opening and the second opening is greater than or equal to 25μm (Zhang et al. teach this distance is a variable balanced between the first opening and the second opening. The second opening (via hole VH12) is located at the junction of the first opening peripheral region 203A and the first display region 2011, where the first signal line changes layers as it enters the first opening peripheral region from the first display region [0098] [0099]. Zhang et al. also teach that the first signal lines bypass the first opening 201A and passes through the first opening peripheral region 203A [0058]. Zhang et al. also teach to leave room for the signal line to run between the openings to provide electrical signals (such as scan signals, data signals, etc.) to the passing sub-pixels [0058]. The first opening and the second opening must therefore be separated by enough distance for the lead portion of the first signal line to run through the first opening peripheral region between them. Therefore, the efficient distance between the openings is a result effective variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, a minimum distance between the first opening and the second opening is greater than or equal to 25μm in order to leave room for the signal line to run between the openings to provide electrical signals (such as scan signals, data signals, etc.) to the passing sub-pixels as taught by Zhang et al. [0058]. MPEP 2144.05. Additionally, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, the applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed distance).
Regarding claim 10, Kim et al. teach the array substrate, wherein
the array substrate comprises a display area (fig. 1, element DA [0045]) and a non-display area (fig. 1, element NDA [0045]) at least partially surrounded (fig. 1 element DA surrounded by NDA) around the display area.
Kim et al. do not explicitly teach the first opening is located in the non-display area;
the first opening is configured to accommodate a control chip; and/or the first conductive part comprises a fanout line.
The exact positioning of the opening (outside the display area) as disclosed by Kim et al. is a design choice that a person skilled in the art could set as appropriate taking into consideration design dimensions, signal wiring and the like. See In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
However, Zhang et al. teach the first opening (figs. 2A-2C element 201A [0054]) is configured to accommodate a control chip (photo electric sensing devise such as camera [0057]);
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filling date of the claimed invention to modify the array substrate of Kim et al. as taught by Zhang et al. in order to accommodate a control chip such as a photo electric sensing devise in the opening so as to realize functions such as light sensing, image shooting and distance sensing [0057].
Regarding claim 11, Kim et al. teach all the limitations as discussed above.
Kim et al. do not teach a minimum distance between the first conductive part and the first opening is greater than or equal to 8μm.
Kim et al. as modified by Zhang et al. teach,
a minimum distance between the first conductive part and the first opening is greater than or equal to 8μm (Zhang et al. teach a barrier wall located in the first opening peripheral region 203A which at least partially surrounding the first opening 201A and at least partially overlapping the first signal line and the second signal line in the direction perpendicular to the base substrate [0077], Zhang et al. teach the barrier wall maintain the stability of the opening peripheral region 203A, maintain the stability of first opening 201A, protects the photoelectric sensing apparatuses in the first opening 201A and preventing water vapor and oxygen from diffusion in to the display region through the first opening [0077]. The signal lines are therefore routed at the position of the barrier wall that surrounds the first opening, at a distance from the first opening determined by the width and placement of that wall. Therefore, the efficient distance between the conductive part and the opening is a result effective variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, a minimum distance between the first conductive part and the first opening is greater than or equal to 8μm in order to route the conductive part at the position of the barrier wall around the opening while keeping the first opening peripheral region small as taught by Zhang et al [0077]. MPEP 2144.05. Additionally, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, the applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed distance).
Regarding claim 12, Kim et al. teach all the limitations as discussed above.
Kim et al. modified by the Zhang et al. teach the number of the first conductive part is plural (fig. 2B of Zhang, elements 2301, 2302, 2303, 2304, 2305, 2306 [0060]),
a minimum distance between two adjacent first conductive parts is greater than or equal to 4μm (However, Zhang et al. teaches reducing the arrangement distance of the signal line and minimizing the area occupied by the region as much as possible [0180]. Therefore, the efficient distance between two adjacent conductive parts is a result effective variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, a minimum distance between two adjacent first conductive parts is greater than or equal to 4μm in order to keep the plurality of lines reliably separated while keeping the area occupied by the first opening peripheral region as small as possible as taught by Zhang et al. [0180]. MPEP 2144.05. Additionally, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, the applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed distance).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIFUR RAHMAN whose telephone number is (571) 895-1534. The examiner can normally be reached on Monday-Friday, 9:00 AM - 5:00 PM (Eastern Time). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/ARIFUR RAHMAN/
Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813
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