Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Application
This action is in response Applicant’s filing on 23 April 2024. Claims 1-16 are presently pending and under consideration.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8 February 2024 and 9 April 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claim 13 is objected to because of the following informalities: “a plurality of second monitors configured to measuring” appears to be incorrect and should recite “a plurality of second monitors configured to measure”. Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: “a first monitor configured to measure” and “a plurality of second monitors configured to measuring” in claim 13 and “a third monitor configured to measure” and “a plurality of fourth monitors to measure” in claim 14.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
A review of the specification discloses the following portions which appear to cover the corresponding structure that performs the claimed function and equivalents thereof: Fig. 1, disclosing monitor 110, Fig. 2, disclosing monitor 110 and monitors 120, monitor 210 and plurality of monitors 220, paragraph [0033], disclosing the monitors 110, 120, 210, and 220 may be implemented using hardware such as circuits.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitations to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Independent claims 1, 13, and 15 and dependent claims 2-12, 14, and 16 are rejected under 35 USC 101 because the claimed invention is directed to a judicial exception of an abstract idea without significantly more. The claims recite estimating a memory latency by using a plurality of first coefficients and indexes to perform a first weight calculation to generate a first estimated latency, adjusting the plurality of first coefficients to generate a plurality of updated first coefficients; using the plurality of updated first coefficients and the plurality of first indexes to perform the first weighted calculation to adjust the first estimated latency for the first estimated latency to approximate the first access latency; and using the plurality of updated first coefficients and a plurality of second indexes of the first memory to perform a second weighted calculation to generate a second estimated latency for a second access operation, as in independent claims 1 and 13, and obtaining a relationship between a plurality of first indexes of a first memory and a plurality of second indexes of a second memory; and generating a plurality of second coefficients for the second memory according to the relationship and a plurality of first coefficients of the first memory, as in independent claim 15.
The limitations of using a plurality of first coefficients and indexes to perform a first weight calculation to generate a first estimated latency, adjusting the plurality of first coefficients to generate a plurality of updated first coefficients; using the plurality of updated first coefficients and the plurality of first indexes to perform the first weighted calculation to adjust the first estimated latency for the first estimated latency to approximate the first access latency; and using the plurality of updated first coefficients and a plurality of second indexes of the first memory to perform a second weighted calculation to generate a second estimated latency for a second access operation, as in independent claims 1 and 13, and obtaining a relationship between a plurality of first indexes of a first memory and a plurality of second indexes of a second memory; and generating a plurality of second coefficients for the second memory according to the relationship and a plurality of first coefficients of the first memory, as in independent claim 15, under its broadest reasonable interpretation, covers performance of the limitation entirely in the mind or merely a mathematical calculation but for the recitation of generic computer components (i.e. first memory, second memory, a memory access latency estimation system, and first monitor and second monitors structurally interpreted above as circuits, and a processor). That is, other than reciting a first memory, a second memory, a system, and first and second monitors structurally interpreted above as circuits, and a processor, nothing in the claim elements precludes the steps from practically being performed in the mind or merely a mathematical calculation. In this instance, a plurality of first coefficients and indexes are used to perform a first weight calculation to generate a first estimated latency, the plurality of first coefficients are adjusted to generate a plurality of updated first coefficients, the plurality of updated first coefficients and the plurality of first indexes are used to perform the first weighted calculation to adjust the first estimated latency for the first estimated latency to approximate the first access latency, the plurality of updated first coefficients and a plurality of second indexes are used to perform a second weighted calculation to generate a second estimated latency for a second access operation, as in independent claims 1 and 13, and a relationship between the plurality of first indexes of a first memory and a plurality of second indexes of a second memory are obtained and used to generate a plurality of second coefficients for the second memory according to the relationship and a plurality of first coefficients of the first memory, as in independent claim 15. If a claim limitation under its broadest reasonable interpretation covers performing of the limitation in the mind but for the recitation of generic computer components, then it falls within the “mental processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, claim 1 recites the additional elements of a “first memory”, claim 13 recites the additional elements of “a memory access latency estimation storage system”, a “first monitor”, a “first memory”, a “plurality of second monitors”, and a “processor”, and claim 15 recites the additional elements of a “first memory”, and a “second memory” which are recited at a high level of generality (i.e. generic computer components performing generic computer functions), such that they amount to no more than mere instructions to apply the exception using generic computer components. The additional elements of the “first access operation”, “second access operation”, “measuring” and “measuring” steps of claim 1, the “first access operation”, “second access operation”, “measure”, and “measuring” steps of claim 13, and the “measuring” and “measuring” steps of claim 15 are mere data gathering and output, which amounts to insignificant extra-solution activity (See MPEP 2106.05(g)). Accordingly, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on performing the abstract idea entirely in the mind.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of a “first memory”, as in claim 1, “a memory access latency estimation storage system”, a “first monitor”, a “first memory”, a “plurality of second monitors”, and a “processor”, as in claim 13, and the additional elements of a “first memory”, and a “second memory”, as in claim 15, amount to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept. Further, the additional elements of the “first access operation”, “second access operation”, “measuring”, and “measuring” steps of claims 1, “first access operation”, “second access operation”, “measure” step, and “measuring” step of claim 13, and “measuring” and “measuring” step of claim 15 are directed to “storing and retrieving information in memory”, which the courts have found to be well-understood, routine, and conventional activities (See MPEP 2106.05(d)(II)). Thus the claims are not patent eligible.
Dependent claim 2 recites additional elements of a “determining” and “adjusting” step, which covers performance of the limitation entirely in the mind or mathematical calculation. Dependent claims 3 -11, and 16 only recite additional functional elements which do not provide a practical application of the mental process or mathematical calculation.
Dependent claim 12 recites using updated first coefficients to perform a third weighted calculation to generate a third estimate latency and adjusting the first coefficients to generate a plurality of second coefficients, and using the plurality of second coefficients and the plurality of third indexes to perform the third weighted calculation to adjust the third estimated latency for the third estimated latency to approximate the second access latency and estimating a group of coefficients corresponding to the second memory according to another group of coefficients corresponding to the first memory and the relationship, and dependent claim 14 similarly recites use the plurality of updated first coefficients and the plurality of third indexes to perform a third weighted calculation to generate a third estimated latency, adjust the plurality of updated first coefficients to generate a plurality of second coefficients, use the plurality of second coefficients and the plurality of third indexes to perform the third weighted calculation to adjust the third estimated latency for the third estimated latency to approximate the second access latency and estimate a group of coefficients corresponding to the second memory according to another group of coefficients corresponding to the first memory and the relationship, which, under its broadest reasonable interpretation, covers performance of the limitation entirely in the mind or merely a mathematical calculation but for the recitation of generic computer components (i.e. first and second memory, as in dependent claim 12, and first and second memory, third monitor, and plurality of fourth monitors, interpreted as circuits, as in dependent claim 14).
It is not integrated into a practical application as the additional elements of a “first memory” and “second memory”, as in claim 12, and “first memory”, “second memory”, “third monitor” and “plurality of fourth monitors” are recited at a high level of generality (i.e. generic computer components performing generic computer functions), such that they amount to no more than mere instructions to apply the exception using generic computer components. The additional elements of the “measuring”, “third access operation”, “measuring” and “storing” steps of claim 12 and “measure”, “third access operation”, “measure”, and “storing” steps of claim 14 are mere “data gathering and output”, which amounts to insignificant extra-solution activity (See MPEP 2106.05(g)). Accordingly, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on performing the abstract idea entirely in the mind.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of a “first memory”, a “second memory” in claim 12 and a “first memory”, a “second memory”, a “third monitor” and a “plurality of fourth monitors” amount to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using generic computer components cannot provide an inventive step. Further, the additional elements of a “measuring” step, a “third access operation”, a “measuring” step, and a “storing” step of claim 12 and a “measure” step, a “third access operation”, a “measure” step, and “storing” step of claim 14 are directed to “storing and retrieving information in memory” which the courts have found to be well-understood routine, and conventional activities (See MPEP 2016.05(d)(II)). The dependent claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception and therefore are also patent ineligible.
Allowable Subject Matter
Claims 1-16 would be allowable if the rejection under 35 USC 101 were to be overcome.
The following is an examiner’s statement of reasons for allowance: A search of the prior art returned the following closest art:
(1) Rayaprolu et al (US 2024/0055046 A1) discloses a model for predicting memory system performance by performing a first set of read operations at a memory device and generating information indicating a performance of the memory device and updating one or more coefficients of a model that correlates the information with a change in a read window.
(2) Fitzpatrick et al (US 11133083 B1) discloses a system configured to transmit read commands, the read commands configured to instruct the memory device to retrieve data from the group of memory cells, wherein a calibration circuit is configured to measure signal and noise characteristics of the group of memory cells during execution of the read commands and wherein, based on the signal and noise characteristics measured during the execution of the read commands, the memory sub-system is configured to generate or update a model of changes relevant to reading data from the group of memory cells.
(3) Li et al (Statistical DRAM Modeling, MEMSYS ’19: Proceedings of the International Symposium on Memory Systems, September 2019) discloses a DRAM timing model exploiting temporal and spatial locality for feature extraction and training and inference flow to provide an atomic interface returning latency of a memory request upon inquiry.
However, the prior art alone or in combination fails to teach or fairly suggest the combination of:
Measuring a first access latency of a first access operation of a first memory, measuring a plurality of first indexes of the first memory corresponding to the first access operation; using a plurality of first coefficients and the plurality of first indexes to perform a first weighted calculation to generate a first estimated latency; adjusting the plurality of first coefficients to generate a plurality of updated first coefficients; using the plurality of updated first coefficients and the plurality of first indexes to perform the first weighted calculation to adjust the first estimated latency for the first estimated latency to approximate the first access latency; and using the plurality of updated first coefficients and a plurality of second indexes of the first memory to perform a second weighted calculation to generate a second estimated latency for a second access operation, where the number and types of the plurality of first and second indexes are the same, the second indexes are corresponding to the second access operation, and the first access operation precedes the second access operation, as in independent claim 1 and similarly in independent claim 13.
Nor does the prior art alone or in combination teach or fairly suggest the combination of:
A memory access latency estimation method by measuring a plurality of first indexes of a first memory, measuring a plurality of second indexes of a second memory; obtaining a relationship between the plurality of first indexes of the first memory and the plurality of second indexes of the second memory; and generating a plurality of second coefficients for the second memory according to the relationship and a plurality of first coefficients of the first memory; wherein the plurality of second coefficients are used to estimate an access latency of the second memory, where the number and the types of the plurality of first and second indexes are the same, as in independent claim 15.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDMUND H KWONG whose telephone number is (571)272-8691. The examiner can normally be reached Monday-Friday 10-6 PT.
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/E.H.K/Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137