Prosecution Insights
Last updated: October 02, 2026
Application No. 18/642,919

SEMICONDUCTOR OPTICAL AMPLIFICATION ELEMENT

Non-Final OA §102§103
Filed
Apr 23, 2024
Priority
May 31, 2023 — JP 2023-090488
Examiner
DECARIA, MICHAEL ALEX
Art Unit
Tech Center
Assignee
NEC Corporation
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds

Examiner Intelligence

Grants only 0% of cases
0%
Career Allowance Rate
0 granted / 0 resolved
-60.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
Avg Prosecution
13 currently pending
Career history
4
Total Applications
across all art units
This examiner has no resolved cases yet (career too new); statute-level performance unavailable. The Grant Probability card shows Tech Center averages instead.

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Examiner acknowledges Applicant’s priority to foreign application JP 2023-090488 filed on 05/31/2023 in Japan. Information Disclosure Statement All references considered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Akiyama (JP 2017098362 A, description translation from Espacenet, figures from original). Regarding Claim 1, Akiyama discloses A semiconductor optical amplification element comprising [Fig. 7]: a first optical amplification waveguide configured to amplify light by using a semiconductor [0048, #4 of Fig. 7]; a second optical amplification waveguide configured to amplify light by using the semiconductor [0048, #5 of Fig. 7]; and a loop waveguide reflector configured to reflect light by using a loop of a waveguide [0046, #7 of Fig. 7, shown as diffraction grating mirror; 0038, loop mirror and diffraction grating mirror interchangeable and non-limiting], wherein one end of the first optical amplification waveguide is connected to the loop waveguide reflector [0048, #7 connected to #4 in Fig. 7], another end of the first optical amplification waveguide and another end of the second optical amplification waveguide are formed with a coplanar anti-reflection termination surface [0049, #4 and #5 connect to same surface of #6 in Fig. 7; 0030, anti-reflection applied to #6 where #4-5 connect; #6 appears in all embodiments], and one end of the second optical amplification waveguide is formed with an anti-reflection termination surface [0049, #5 connects to #11 in Fig. 7; 0030, anti-reflection]. Regarding Claim 2, Akiyama discloses The semiconductor optical amplification element according to claim 1, wherein the first optical amplification waveguide is formed on the same semiconductor chip as the second optical amplification waveguide [0025, #4-5 mounted on #1 in all embodiments, including Fig. 7]. Regarding Claim 3, Akiyama discloses The semiconductor optical amplification element according to claim 1,wherein another end of the first optical amplification waveguide is connected to a wavelength variable filter [0047, #4 connected to #10 in Fig. 7, #10 is vernier-type wavelength filter]. Regarding Claim 4, Akiyama discloses The semiconductor optical amplification element according to claim 1, wherein the first optical amplification waveguide is a laser semiconductor optical amplifier [0050, #4 connected to #10 in Fig. 7], and the second optical amplification waveguide is an optical output semiconductor optical amplifier [0050, #5 connected to #11 in Fig. 7]. Regarding Claim 5, Akiyama discloses The semiconductor optical amplification element according to claim 4, wherein the first optical amplification waveguide is connected to the second optical amplification waveguide [0025, #4-5 connected via #1, optically connected]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: Determining the scope and contents of the prior art. Ascertaining the differences between the prior art and the claims at issue. Resolving the level of ordinary skill in the pertinent art. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Akiyama (JP 2017098362 A, translation from Espacenet) as applied to claim 1 above, and further in view of Krishnamoorthy (US 2019/0027899). Regarding Claims 6 and 7, Akiyama teaches The semiconductor optical amplification element according to claim 1, wherein the loop waveguide reflector [0038, 0046, #7 of Fig. 7 can be loop waveguide reflector] is connected to the one end of the first optical amplification waveguide by using a 1×2 coupler [0033]. However, Akiyama does not explicitly teach a specific type of coupler. Krishnamoorthy teaches various 1×2 couplers are interchangeable in an optical source with an optical gain chip [0043, #118 in Fig. 1A can be a Y-junction splitter, a directional coupler (Claim 6), a 1×2 multi-mode interference coupler (Claim 7), a photonic crystal splitter, etc.]. It would have been obvious to one of ordinary skill in the optical amplification arts prior to the effective filing date of the claimed invention to try any 1×2 coupler or splitter of Krishnamoorthy to couple the loop waveguide reflector to the one end of the first optical amplification waveguide in Akiyama with a reasonable expectation of success. Relevant Prior Art In addition to teaching the particular arrangement of components in the claimed invention, Akiyama teaches other arrangements, e.g. the loop mirror integrated into the wavelength tuner on a same side of an SOA (#7 and #10 in Fig. 1A; Figs. 5-6 and 9 show #7 is #10D), so the claimed invention does not prima facie represent the only arrangement of components to achieve the desired effect. Examiner further identified the following relevant prior art: Jackel (US 2011/0182587) discloses forming a loop mirror coupled to the rest of the network using a splitter [0039]. Any standard splitter can do this, including the Y-splitter taught by Krishnamoorthy above. Matsumoto (JP 2019053204) discloses a wavelength tunable laser with a similar design to the claimed invention [Fig. 9], though a loop mirror is visibly absent from the one end of the first SOA [#32 of Fig. 9]. Disclosures of wavelength tunable lasers are generally useful. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALEX DECARIA whose telephone number is (571)270-0565. The examiner can normally be reached Monday-Thursday, 6:45 a.m. - 5:15 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Helal Algahaim can be reached at (571) 270-5227. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MAD/Examiner, Art Unit 3645 /HELAL A ALGAHAIM/SPE , Art Unit 3645
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Prosecution Timeline

Apr 23, 2024
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allowance rate.

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