DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
1. Claim 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 115951750 A – cited in IDS filed on 4/23/2024), in view of Wang et al. (CN 112187179 A).
In regard to Claim 1:
Chen discloses, in Figure 1, a voltage buffer, comprising: a first transistor (M1), wherein a gate of the first transistor (M1 gate) is coupled to a first input of the voltage buffer (INP), and a source of the first transistor (M1 source) is coupled to a first output (OUTP) of the voltage buffer; a first current source (M3) coupled to the source of the first transistor (M1 source); a second transistor (M2), wherein a gate of the second transistor (M2 gate) is coupled to a second input of the voltage buffer (INN), and a source of the second transistor (M2 source) is coupled to a second output of the voltage buffer (OUTN); a second current source (M4) coupled to the source of the second transistor (M2 source); a third transistor (M3), wherein a drain of the third transistor (M3 drain) is coupled to the source of the first transistor (M1 source); a first coupling capacitor (C1) coupled between a gate of the third transistor (M3 gate) and the second input of the voltage buffer (INN); a fourth transistor (M4), wherein a drain of the fourth transistor (M4 drain) is coupled to the source of the second transistor (M2 source); a second coupling capacitor (C2) coupled between a gate of the fourth transistor (M4 gate) and the first input of the voltage buffer (INP).
Chen does not disclose a third current source coupled to a source of the third transistor and a source of the fourth transistor.
In a similar field of endeavor, Wang discloses a third current source (Figure 2, M5) coupled to a source of the third transistor (M1 source) and a source of the fourth transistor (M2 source).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add the third current source taught by Wang coupled to a source of the third transistor and a source of the fourth transistor taught by Chen, to utilize the third current source to serve as a tail current source which provides a stable bias current and improves common-mode rejection ratio for amplifiers.
In regard to Claim 2:
Chen discloses the voltage buffer of claim 1, wherein: a drain of the first transistor (M1 drain) and a drain of the second transistor (M2 drain) are coupled to a supply rail; the first current source (M3) is coupled between the source of the first transistor (M1 source) and a ground; the second current source (M4) is coupled between the source of the second transistor (M2 source) and the ground.
Chen does not disclose the third current source coupled between the source of the third transistor and the supply rail; and the third current source is coupled between the source of the fourth transistor and the supply rail.
In a similar field of endeavor, Wang discloses the third current source (M5) is coupled between the source of the third transistor (M1 source) and the ground; and the third current source (M5) is coupled between the source of the fourth transistor (M2 source) and the ground.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to add the third current source taught by Wang coupled to a source of the third transistor and a source of the fourth transistor taught by Chen, to utilize the third current source as a tail current source which provides a stable bias current and improves common-mode rejection ratio for amplifiers.
In regard to Claim 3:
Chen further discloses, the voltage buffer of claim 2, wherein each of the first transistor (M1), the second transistor (M2), the third transistor (M3), and the fourth transistor (M4) comprises a respective n-type field effect transistor (NFET).
In regard to Claim 4:
Chen discloses the voltage buffer of claim 1, wherein: a drain of the first transistor (M1) and a drain of the second transistor (M2) are coupled to a ground indirectly (ref voltage); the first current source (M3) is coupled between the source of the first transistor (M1 source) and a supply rail (VDD); the second current source (M4) is coupled between the source of the second transistor (M2 source) and the supply rail (VDD) indirectly.
Chen does not disclose the third current source coupled between the source of the third transistor and the supply rail; and the third current source is coupled between the source of the fourth transistor and the supply rail.
In a similar field of endeavor, Wang discloses the third current source (M5) is coupled between the source of the third transistor (M1 source) and the supply rail; and the third current source (M5) is coupled between the source of the fourth transistor (M2 source) and the supply rail (VDD).
It would have been obvious to one having ordinary skill in the art, before the effective filing date, to add the third current source coupled between the source of the third transistor and the supply rail and coupled between the source of the fourth transistor and the supply rail, to utilize the third current source which provides a stable bias current and improves common-mode rejection ratio for amplifiers.
2. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (CN 115951750 A) in view of Wang (CN 112187179 A) as applied to claim 4 above, and further in view of Sutardja (US 7,7245,96 B1).
In regard to Claim 5:
Chen, as modified by Wang, does not disclose the first, second, or third transistors comprising a respective p-type field effect transistor (PFET).
In a similar field of endeavor Sutardja discloses wherein each of the first transistor, the second transistor, third transistor, and the fourth transistor can be interchanged with PMOS/PFET when polarities and states of voltages and signals are reversed (Column 9 lines 11-14).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to make a simple substitution of the NFETs of Chen and Wang for the use PFETs as taught by Sutardja, in order to flip the polarity/power rails which allows you to pull signals up to the positive rail instead of pulling down to ground.
3. Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 115951750 A) in view of Wang et al. (CN 112187179 A) as applied to claim 5 above, and further in view of Vera Villarroel et al. (US 10,965,252).
In regard to Claim 6:
Chen, as modified by Wang, does not teach the third current source comprising a programmable current source.
In a similar field of endeavor Vera Villarroel discloses wherein the third current source (I1b) comprises a programmable current source (paragraph 20 line 8).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the current source taught by Vera Villarroel with the amplifier taught by Chen and Wang, in order to form a third current source comprising a programmable current source, allowing for precise control over said voltage buffer.
In regard to Claim 7:
Chen, as modified by Wang, does not teach the additions of a first current source and second current source comprising a respective programmable current source.
In a similar field of endeavor Vera Villarroel discloses a current source comprising a programmable current source (Figure 4, I1b).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the current source taught by Vera Villarroel with the amplifier taught by Chen and Wang, in order to increase the voltage of the first terminal, e.g. base, of the respective auxiliary transistors, thereby extending the linear region of the transfer function of the last stage amplifier and the driver (Vera Villarroel Column 5: lines 13-23).
4. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 115951750 A) in view of Wang et al. (CN 112187179 A) as applied to claims 6-7 above, in further view of Clara et al. (US 11489536 B1).
In regard to Claim 8:
Chen, in view of Wang, does not disclose the voltage buffer of claim 1 coupled to a first input of analog-to-digital (ADC), and the second output of the voltage buffer is coupled to a second input of the ADC.
In a similar field of endeavor Clara discloses, in Figure 3, wherein the first output of the voltage buffer (307; inverting output) is coupled to a first input of an analog-to-digital converter (ADC) (101), and the second output of the voltage buffer (307; non-inverting output) is coupled to a second input of the ADC (101).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to couple the two outputs of the voltage buffer, as taught by Chen and Wang, to the two inputs of an ADC as taught by Clara, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385).
5. Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 115951750 A) in view of Wang et al. (CN 112187179 A) as applied to claim 8 above, in further view of Hester et al. (US 4843342 A).
In regard to Claim 9:
Chen, in view of Wang, does not disclose the first current source comprises a fifth transistor, the second current source comprises a sixth transistor, the third current source comprises a seventh transistor, and the voltage buffer further comprises a bias circuit configured to bias a gate of the fifth transistor, a gate of the sixth transistor, and a gate of the seventh transistor.
In a similar field of endeavor Hester discloses, in Figure 1, wherein the first current source comprises a fifth transistor (Q3), the second current source comprises a sixth transistor (Q4), the third current source comprises a seventh transistor (Q12), and the voltage buffer comprises a bias circuit (Q11) configured to bias a gate of the fifth transistor (Q3), a gate of the sixth transistor (Q4), and a gate of the seventh transistor (Q12).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to use the transistor current sources taught by Hester with the current sources taught by Chen and Wang, because utilizing transistors as current sources provide a steady current flow despite changes in load resistance and supply voltages.
In regard to Claim 10:
Chen, in view of Wang, does not disclose the bias circuit comprises: a reference current source; and an eighth transistor, wherein a drain of the eighth transistor is coupled to the reference current source, and a gate of the eighth transistor is coupled to the drain of the eighth transistor, the gate of the fifth transistor, the gate of the sixth transistor, and the gate of the seventh transistor.
In a similar field of endeavor Hester discloses the bias circuit comprising: a reference current source (Q9); and an eight transistor (Q11), wherein a drain of the eight transistor (Q11 drain) is coupled to the reference current source (Q9), and a gate of the eight transistor (Q11 gate) is coupled to the drain of the eight transistor (Q11 drain), the gate of the fifth transistor (Q3 gate), the gate of the sixth transistor (Q4 gate), and a gate of the seventh transistor (Q12 drain).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize a bias circuit taught by Hester with the current sources taught by Chen and Wang, allowing to bias the transistors as current sources as current sources as current sources provide a steady current flow despite changes in load resistance and supply voltages.
6. Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 115951750 A) in view of Wang et al. (CN 112187179 A).
In regard to Claim 11:
Chen discloses, in Figure 1, a voltage buffer, comprising: a first source follower (M1) having an input and an output; a second source follower (M2) having an input and an output; a first transistor (M3), wherein a drain of the first transistor (M1 drain) is coupled to the output of the first source follower (M1); a first coupling capacitor (C1) coupled between a gate of the first transistor (M1 gate) and the input of the second source follower (M2); a second transistor (M4), wherein a drain of the second transistor (M4 drain) is coupled to the output of the second source follower (M2); a second coupling capacitor (C2) coupled between a gate of the second transistor (M2 gate) and the input of the first source follower (M1).
Chen does not disclose the current source coupled to a source of the first transistor and a source of the second transistor.
Wang discloses a current source (M5) coupled to a source of the first transistor (M1 source) and a source of the second transistor (M2 source).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add the third current source taught by Wang coupled to a source of the third transistor and a source of the fourth transistor taught by Chen, to utilize the third current source to serve as a tail current source which provides a stable bias current and improves common-mode rejection ratio for amplifiers.
7. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 115951750 A) in view of Wang et al. (CN 112187179 A) as applied to claim 11 above, in further view of Vera Villarroel et al. (US 10965252 B2).
In regard to Claim 12:
Chen, in view of Wang, does not disclose wherein the current source comprises a programmable current source.
In a similar field of endeavor Vera Villarroel discloses wherein the current source (I1b) comprises a programmable current source (paragraph 20 line 8).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the current source taught by Vera Villarroel with the amplifier taught by Chen and Wang, in order to form a third current source comprising a programmable current source, allowing for precise control over said voltage buffer.
8. Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 115951750 A) in view of Wang et al. (CN 112187179 A) as applied to claim 12 above, in further view of Clara et al. (US 11489536 B1).
In regard to Claim 13:
Chen, in view of Wang, does not disclose wherein the first output of the voltage buffer is coupled to a first input of an analog-to-digital converter (ADC), and the second output of the voltage buffer is coupled to a second input of the ADC.
In a similar field of endeavor Clara (US 11489536B1) discloses, in Figure 3, wherein the first output of the voltage buffer (307) is coupled to a first input of an analog-to-digital converter (ADC) (101), and the second output of the voltage buffer (307) is coupled to a second input of the ADC (101).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the ADC connection to the voltage buffer, as taught by Clara, in combination with the voltage buffer taught by Chen and Wang, as a simple substitution of known elements to yield predictable results.
9. Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 115951750 A) in view of Wang et al. (CN 112187179 A) as applied to claim 12 above, in further view of Hester et al. (US 4843342 A).
In regard to Claim 14:
Chen, in view of Wang, does not disclose the current source comprising a third transistor (Q3), and the voltage buffer comprises a bias circuit (Q11) configured to bias the third transistor (Q3).
In a similar field of endeavor Hester discloses wherein the current source comprises a third transistor (Q3), and the voltage buffer comprises a bias circuit (Q11) configured to bias the third transistor (Q3).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize a current source comprising a third transistor, in addition to the bias circuit, as taught by Hester, in combination with the voltage buffer taught by Chen and Wang, as the third transistor provides a stable current source and the bias circuit provides a stable method of biasing said transistor.
In regard to Claim 15:
Chen, in view of Wang, does not disclose the bias circuit comprising a reference current source; and a fourth transistor, wherein a drain of the fourth transistor is coupled to the reference current source, and a gate of the fourth transistor is coupled to the drain of the fourth transistor and the gate of the third transistor.
In a similar field of endeavor Hester discloses wherein the bias circuit comprises:
A reference current source (Q9); and a fourth transistor (Q11), wherein a drain of the fourth transistor (Q11 drain) is coupled to the reference current source (Q9), and a gate of the fourth transistor (Q11 gate) is coupled to the drain of the fourth transistor (Q11) drain) and the gate of the third transistor (Q3 gate).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize a bias circuit comprising a reference current made of a fourth transistor, as taught by Hester, for biasing the third transistor as it provides a stable current source and the bias circuit provides a stable method of biasing said transistor.
10. Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 115951750 A) in view of Wang et al. (CN 112187179 A), in further view of Vera Villarroel et al. (US 10965252 B2).
In regard to Claim 16
Chen discloses a voltage buffer (Figure 1), wherein the voltage buffer includes and first source follower (M1) and a second source follower (M2).
Chen does not disclose the method for operating said volage buffer.
In a similar field of endeavor Vera Villarroel discloses, in Figure 2, wherein steering a current of a current source to the first source follower (Q3) during a first time period in which the second input voltage (INN) is greater than he first input voltage (INP); and steering the current of the current source to the second source follower (Q4) during a second time period in which the first input voltage (INP) is greater than the second input voltage (INN).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to operate the voltage buffer wherein the voltage buffer includes a first source follower (M1) and a second source follower (M2), as taught by Chen, wherein during a first time period, the second input voltage is greater than the first input voltage steering current to the first source follower and a second time period in which the first input voltage is greater than the second input voltage steering current to the second current source, as taught by Vera Villarroel, in order to extend the linear output voltage range of a driver, and reduce the power consumption. (Vera Villaroel Column 2: lines 17-19).
In regard to Claim 17:
Chen further discloses driving an input of the first source follower (M1) with the first input voltage (INP) and driving an input of the second source follower (M2) with the second input voltage (INN).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMAAN JAWAD KHAN whose telephone number is (571)270-7266. The examiner can normally be reached M-Th 9-4.
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/AMAAN JAWAD KHAN/Examiner, Art Unit 2843
/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
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