DETAILED ACTION
This Office action is in response to the application filed on 23 April 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 9-15, 17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Viswanathan et al. (US Patent 10,128,744; “Viswanathan”).
In re claims 1, 9 and 14, Viswanathan discloses an apparatus and system for power conversion (see Figs. 1-3) comprising:
a switch controller (Figs. 1, 2: 102) couplable to a power converter circuit (Fig. 1: 100) including one or more drivers (Fig. 1: each one of the phase circuits, e.g. comprising switch 140 and diode 138, constitutes a driver) configured to couple a power source to an energy storage device that is coupled to a load (Fig. 1: for instance when switch 140 is turned on, current flows through inductor 132, thus coupling it to power source 106, 108, 110; inductor 132 is further coupled to load 104 through diode 138) , wherein the switch controller is configured to cause charging or discharging of the power converter circuit (see Fig. 4, graph 420 showing charging/discharging cycles of the inductor);
a first counter circuit (Fig. 3: 304) configured to receive an indication that the switch controller circuit has caused charging or discharging (Fig. 3: counter 304 receives signal GDA, indicating charging and discharging of the inductor; see col. 4 lines 56-63, and see Fig. 4: graphs 400 and 420), wherein the first counter circuit is configured to measure a first time period indicating an amount of time the switch controller circuit has caused charging or discharging for a predetermined number of charge/discharge cycles (col. 8 lines 20-25: “A second counter 304 counts the number of CLK signal cycles during which the GDA signal is high in the switching control cycle N, and outputs a second count value TON that represents the controlled on time TON for the first switching control cycle N”);
a second counter circuit (Fig. 3: 302) configured to receive an indication that the switch controller circuit has caused charging or discharging (Fig. 3: counter 302 receives signal GDA indicating charging and discharging of the inductor; see col. 4 lines 56-63, and see Fig. 4: graphs 400 and 420), wherein the second counter circuit is configured to measure a second time period indicating a total amount of time in the predetermined number of charge/discharge cycles (col. 8 lines 7-18: “a first counter 302 that counts the number of cycles of the clock signal CLK between a rising edge of the first switching control signal GDA and a rising edge of the zero current detection signal ZCDA … outputs a first count value TIC.sub.N that represents the inductor conduction time … TIC.sub.N includes the on time of the converter switch 140 (TON) during which the inductor current I.sub.L1 increases (e.g., charging time), as well as the discharge time TDC”); and
a load computation circuit (remaining circuit of Fig. 3; or more generally, processor 202 and memory 208 in Fig. 2) coupled to the first counter circuit and the second counter circuit, wherein the load computation circuit is configured to:
determine a duty cycle based on the first time period and the second time period (see Fig. 5, step 512 and see col. 10 lines 55-58: “computing the duty cycle D.sub.N of the present control cycle N at 512 according to the on time TON.sub.N and the determined inductor conduction time TIC.sub.N”); and
adjust how often the switch controller circuit causes charging or discharging based on the determined duty cycle (see Fig. 5, steps 514-524 and see col. 11 lines 27-32: “the processor 202 sets the controlled on time TON and the controlled off time TDC+TDCM for the second switching control cycle N+1 according to the computed first time value TON.sub.N+1 and the computed threshold time value TCR.sub.N at 508-524 in FIG. 5”; it is noted that TCR is the critical time calculated based on the duty cycle in step 514, and TDCM is the DCM/deadtime added onto the switching cycle that will determine “how often” the charging/discharging occurs).
In re claims 2 and 15, Viswanathan discloses wherein the first time period and the second time period are measured based on a number of clock cycles (see Fig. 3: clock inputs CLK to the counters 302 and 304; see also paragraph beginning at col. 8 line 4).
In re claims 3 and 16, Viswanathan discloses wherein the predetermined number of charge/discharge cycles is configurable (Fig. 4: burst mode operation; see col. 13 lines 30-34: “the control circuit 102 operates in burst mode 604 during which one or more control cycles are effectively skipped by keeping both switches 140 and 160 off”).
In re claims 4 and 17, Viswanathan discloses wherein the duty cycle is determined by dividing the first time period by the second time period (Fig. 5: step 512).
In re claim 10, Viswanathan discloses wherein the charge/discharge cycle comprises at least one charge cycle for charging the energy storage device, one discharge cycle for discharging the energy storage device, and a deadtime where the energy storage device is neither charged nor discharged (Fig. 4, graph 420: in DCM mode (middle of graph): TCYCLE=TON+TDC+TDCM, that is, a full cycle comprises charging cycle TON, discharging cycle TDC, and deadtime TDC).
In re claim 11, Viswanathan discloses wherein the deadtime comprises neither charging nor discharging the energy storage device for more than a predetermined amount of time (see Fig. 4: TDCM; and see col. 7 lines 17-20: “For DCM operation, the PWM circuit 170 waits an additional discontinuous mode off time TDCM.sub.N+1 after the ZCDA signal indicates the inductor current has reached zero”; and see col. 11 lines 46-50: “processor 202 computes the additional discontinuous mode off time TDCM.sub.N+1 at 524 according to the difference between the first time value TON.sub.N+1 and the threshold time value TCR.sub.N (e.g., according to (TON.sub.N+1−TCR.sub.N)”; TDCM is always more than the predetermined minimum amount of time, which is zero when TON=TCR).
In re claims 12 and 20, Viswanathan discloses a comparator coupled to an output of the power converter circuit (Fig. 2: comparator 212, with VSENSE input coupled to output VO through resistor 164), wherein the comparator is configured to:
compare an output voltage (VO, as represented by VSENSE) of the power converter circuit and a reference voltage (VREF) to determine that the output voltage has dropped below the reference voltage (see col. 11 lines 7-10: “the control circuit 102 includes the amplifier 212 (FIG. 2) that compares the reference voltage signal VREF with the output voltage feedback signal VSENSE”; and see Fig. 7 and col. 12 lines 57-62: “FIG. 7 includes a graph 700 that shows operation of the DC-DC converter of FIG. 1 in the modes of FIG. 6 is a function of load. The control circuit in one example implements the thresholds 701-706 with respect to the output voltage feedback signal VSENSE”); and
adjust how often the switch controller circuit causes charging or discharging based on the determination that the output voltage has dropped below the reference voltage (Fig. 7: when VSENSE drops into DCM or burst mode regions, the TDCM is computed as shown in Fig. 5, step 524 and explained above).
In re claim 13, Viswanathan discloses wherein, to adjust how often the switch controller circuit causes charging or discharging based on the determination that the output voltage has dropped below the reference voltage, the comparator is configured to adjust how often the switch controller circuit causes charging or discharging to a maximum setting (See Fig. 4, graph 420: showing charging/discharging cycles where inductor is charged to peak values IPK or IPTH, both of which are considered a maximum setting for their particular mode(s)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Viswanathan in view of “High-speed arithmetic in binary computers” by O.L. MacSorley (hereinafter “MacSorley”).
In re claims 5 and 18, Viswanathan discloses the invention according to claims 1 and 14 as explained above, including that the duty cycle is calculated by way of a division operation (Fig. 5: step 512), but does not further disclose that the duty cycle is determined based on bit shifting. Whereas MacSorley teaches several methods of performing division by binary computers, all of which involve bit-shifting (p. 24, right column, first full paragraph). The methods taught by MacSorley are of varying complexity and speed, but are primarily concerned with reducing the amount of time required to perform a calculation (p. 24, left column, first two paragraphs under “Binary Division”).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system and apparatus of Viswanathan by calculating the duty cycle by performing division using a method that involves bit shifting, such that the computation could be performed on the digital processor of Viswanathan using one of the methods disclosed by MacSorley, to obtain the advantages of reduced computation complexity and time requirements.
Allowable Subject Matter
Claims 6-8 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 6, the closest prior art in Viswanathan, cited and described above in this Office action, discloses the invention according to claim 1. However, Viswanathan does not disclose a burst mode detection circuit configured to receive an indication that the switch controller circuit has caused charging or discharging, wherein the burst mode detection circuit is configured to detect a burst mode based on a number of charge cycles and discharge cycles in a burst cycle. Furthermore, the remaining prior art on record fails to suggest an obvious modification to Viswanathan that would have arrived at the invention as recited in claim 6.
Claims 7-8 depend from claim 6 and so would be allowable for the same reasons given above. Claim 19 recites substantially similar limitations as in claim 6, and thus it would also be allowable for the same reasons as given above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2012/0250378 discloses burst-mode operation of a switching converter using counters for measuring a burst period (Figs. 6-8).
US 2019/0229626 discloses adaptive wakeup time control in burst mode including counting number of pulses in a burst mode (Fig. 5).
US 2020/0266712 discloses a burst mode operation for a resonant converter, using a burst cycle counter (Fig. 8A).
US 2021/0384825 discloses a controller for a power supply including first and second counters for measuring lengths of a total cycle period and a burst cycle period (Fig. 4A).
US 2023/0062534 discloses a power control device and DC-DC converter comprising counters for measuring a burst period and a burst disabled period (Fig. 6).
US 2024/0120838 discloses a DC-DC converter circuit and method of operation using first and second counters to measure skip/burst activity (Fig. 4A).
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/FRED E FINCH III/Primary Examiner, Art Unit 2838