DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 04/23/24 are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brokaw et al. (WO 9641248 A1).
Brokaw et al. disclose a frequency compensation for a low drop out regulator in Figures 1-2.
Regarding claim 1. An integrated circuit (IC) (Figure 1), comprising: an error amplifier (14) having a first input (-), a second input (+), and an output (22); a first resistor (R4) and a second resistor (R3), each having a first terminal and a second terminal; a first transistor (Q2) having a first terminal, a second terminal, and a control terminal, the control terminal of the first transistor (Q2) coupled to the output (22) of the error amplifier (14); a second transistor (Q1) having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor (Q1) coupled to the first terminal of the first transistor (Q2) and the first terminal of the first resistor (R4), and the control terminal of the second transistor (Q1) coupled to the second terminals of the first resistor (R4) and of the second resistor (R3) and to the first input of the error amplifier (14); and a current source (IL) having a first terminal and a second terminal, the first terminal of the current source coupled to the second terminal of the second transistor (Page 6, line 17 to page 8, line 20).
Regarding claim 5. The IC of claim 1, wherein the error amplifier (14) is a ring amplifier.
Regarding claim 12. A system comprising (Figure 1): a control circuit (10) including a reference voltage terminal (16); an error amplifier (14) having a first input (-), a second input (+), and an output (22), the first input of the error amplifier coupled to the reference voltage terminal (16) of the control circuit; a first resistor (R4) and a second resistor (R3), each having a first terminal and a second terminal; a first transistor (Q2) having a first terminal, a second terminal, and a control terminal, the control terminal of the first transistor (Q2) coupled to the output of the error amplifier (22); a second transistor (Q1) having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor (Q1) coupled to the first terminal of the first transistor (Q2) and the first terminal of the first resistor (R4), and the control terminal of the second transistor (Q1) coupled to the second terminals of the first resistor (R4) and of the second resistor (R3) and to the second input of the error amplifier (14); and a current source (IL having a first terminal and a second terminal, the first terminal of the current source coupled to the second terminal of the second transistor (Q1) (Page 6, line 17 to page 8, line 20).
Allowable Subject Matter
Claims 2-4, 6-11 and 13-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 is allowed because the prior art of record fails to disclose or suggest an integrated circuit including the limitation “wherein the current source includes: a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the second terminal of the second transistor; and a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to the second terminal of the third transistor, and the control terminal of the fourth transistor coupled to the second input of the error amplifier“ in addition to other limitations recited therein.
Claim 3 is allowed because the prior art of record fails to disclose or suggest an integrated circuit including the limitation “wherein the current source includes a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the second terminal of the second transistor; and wherein the error amplifier includes a fourth transistor having a first terminal, a second terminal, and a control terminal; further comprising a fifth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor coupled to the control terminals of the third transistor, the fourth transistor, and the fifth transistor“ in addition to other limitations recited therein.
Claim 4 is allowed because the prior art of record fails to disclose or suggest an integrated circuit including the limitation “wherein the current source includes: a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the second terminal of the second transistor; and a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to the second terminal of the third transistor; further comprising: a fifth transistor having a first terminal, a second terminal, and a control terminal; a sixth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the sixth transistor coupled to the control terminals of the third transistor and the fifth transistor; a seventh transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh transistor coupled to the second terminal of the fifth transistor; and an eighth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the eighth transistor coupled to the second terminal of the sixth transistor, and the control terminal of the eighth transistor coupled to the control terminals of the fourth transistor and the seventh transistor“ in addition to other limitations recited therein.
Claim 6 is allowed because the prior art of record fails to disclose or suggest an integrated circuit including the limitation “wherein the error amplifier, the first and second resistors, the first and second transistors, and the current source together form a low dropout voltage regulator that has a dead zone; and wherein the error amplifier includes: a first stage that is a differential amplifier and that is configured to receive the first and second inputs of the error amplifier; a second stage to which a range of the dead zone is responsive; and a third stage configured to provide a gate voltage to the control terminal of the first transistor“ in addition to other limitations recited therein.
Claim 7 is allowed because the prior art of record fails to disclose or suggest an integrated circuit including the limitation “wherein the error amplifier includes: a differential amplifier having a first input, a second input, and an output, the first and second inputs of the differential amplifier respectively coupled to the first and second input of the error amplifier; a second stage having an input, a first output, and a second output, the input of the second stage coupled to the output of the differential amplifier; and a third stage having a first input, a second input, and an output, the first input of the third stage coupled to the first output of the second stage, the second input of the third stage coupled to the second output of the second stage, and the output of the third stage coupled to the control terminal of the first transistor“ in addition to other limitations recited therein.
Dependent claims 8 - 11 are allowable by virtue of their dependency.
Claim 13 is allowed because the prior art of record fails to disclose or suggest a system including the limitation “wherein the current source includes: a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the second terminal of the second transistor; and a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to the second terminal of the third transistor, and the control terminal of the fourth transistor coupled to the second input of the error amplifier“ in addition to other limitations recited therein.
Claim 14 is allowed because the prior art of record fails to disclose or suggest a system including the limitation “wherein the current source includes a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the second terminal of the second transistor; and wherein the error amplifier includes a fourth transistor having a first terminal, a second terminal, and a control terminal; further comprising a fifth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor coupled to the control terminals of the third transistor, the fourth transistor, and the fifth transistor“ in addition to other limitations recited therein.
Claim 15 is allowed because the prior art of record fails to disclose or suggest a system including the limitation “wherein the current source includes: a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the second terminal of the second transistor; and a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to the second terminal of the third transistor; further comprising: a fifth transistor having a first terminal, a second terminal, and a control terminal; a sixth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the sixth transistor coupled to the control terminals of the third transistor and the fifth transistor; a seventh transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh transistor coupled to the second terminal of the fifth transistor; and an eighth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the eighth transistor coupled to the second terminal of the sixth transistor, and the control terminal of the eighth transistor coupled to the control terminals of the fourth transistor and the seventh transistor“ in addition to other limitations recited therein.
Claim 16 is allowed because the prior art of record fails to disclose or suggest a system including the limitation “wherein the error amplifier, the first and second resistors, the first and second transistors, and the current source together form a low dropout voltage regulator that has a dead zone; and wherein the error amplifier includes: a first stage that is a differential amplifier and that is configured to receive the first and second inputs of the error amplifier; a second stage to which a range of the dead zone is responsive; and a third stage configured to provide a gate voltage to the control terminal of the first transistor“ in addition to other limitations recited therein.
Claim 17 is allowed because the prior art of record fails to disclose or suggest a system including the limitation “wherein the error amplifier includes: a differential amplifier having a first input, a second input, and an output, the first and second inputs of the differential amplifier respectively coupled to the first and second input of the error amplifier; a second stage having an input, a first output, and a second output, the input of the second stage coupled to the output of the differential amplifier; and a third stage having a first input, a second input, and an output, the first input of the third stage coupled to the first output of the second stage, the second input of the third stage coupled to the second output of the second stage, and the output of the third stage coupled to the control terminal of the first transistor“ in addition to other limitations recited therein.
Dependent claims 18-20 are allowable by virtue of their dependency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lu et al. (US 10,310,530 B1) disclose a low-dropout regulator with load-adaptive frequency compensation.
Cerchi et al. (US 8,222,877 B2) disclose a voltage regulator and method for voltage regulation.
Cerchi et al. (EP 1947544 A1) disclose voltage regulator and method for voltage regulation.
Examiner has cited particular columns, line numbers and/or paragraphs in thereferences applied to the claims above for the convenience of the applicant. Althoughthe specified citations are representative of the teachings of the art and are applied tospecific limitations within the individual claim(s), other passages and figures may applyas well.
Additionally, in the event that other prior art is provided and made of record by theExaminer, as being relevant or pertinent to applicant's disclosure but not relied upon.The references are provided for the convenience of the applicant. The Examinerrequest that the references be considered in any subsequent amendments, as they arealso representative of the art and may apply to the specific limitations ofany newly amended claim(s).
It is respectfully requested from the applicant in preparing amendments or responses, to fully consider the references in their entirety as potentially teaching all or part of theclaimed invention, as well as the context of the passage as taught by the prior art and/ordisclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied upon inorder to ensure proper interpretation of the newly added limitations and toverify/ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADOLF D BERHANE whose telephone number is (571)272-2077. The examiner can normally be reached 7:00 AM to 4:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached at 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ADOLF D BERHANE/Primary Examiner, Art Unit 2838