DETAILED ACTION
Claims 1-20 are pending.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/2/2026 has been entered.
The office acknowledges the following papers:
Claims and remarks filed on 3/2/2026.
New Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5, 9-11, and 17-18 are rejected under 35 U.S.C. 102(a)(1 & 2) as being anticipated by Lichtenau et al. (U.S. 2022/0405556).
As per claim 1:
Lichtenau disclosed a processing device, comprising:
instruction fetch circuitry (Lichtenau: Figure 1B element 150, paragraph 56);
decoder circuitry coupled to the instruction fetch circuitry (Lichtenau: Figure 1B element 152, paragraph 56); and
neural network operation circuitry coupled to the decoder circuitry (Lichtenau: Figures 1A-1B and 2A elements 104-105, 154, 214, and 218, paragraphs 47, 56, and 59-60);
wherein the instruction fetch circuitry is configured to:
fetch a neural network instruction from a memory (Lichtenau: Figures 1A-B, 2A, and 3A elements 106, 112-116, 120, 150, and 200, paragraphs 50, 56-58, and 67), wherein the neural network instruction specifies:
an operation of a group of operations (Lichtenau: Figures 3B-3C elements 302 and 314, paragraphs 67 and 72)(The function code specifies a select operation to be performed by the neural network processing assist (NNPA) instruction.); and
a set of data (Lichtenau: Figures 3D and 3F-3G elements 320, 365, and 382-388, paragraphs 73, 86, 100-101, 103, and 105-107)(The NNPA instruction specifies multiple input tensors.); and
provide the neural network instruction to the decoder circuitry (Lichtenau: Figures 1B and 2A elements 150-152 and 200, paragraphs 56-58); and
wherein the decoder circuitry is configured to cause the neural network operation circuitry to perform (Lichtenau: Figure 2A elements 200 and 204, paragraph 59), based on the operation, a convolution operation using a first sub-circuit of the neural network operation circuitry and the set of data (Lichtenau: Figures 2A, 2C, 3C, and 3F-G elements 204, 214, 218, 260, 365, and 388, paragraphs 59-60, 64-65, 72, 100, 107, 109, 327-328, and 334-335)(Decoding a NNPA instruction with a convolution function code causes the input tensors to be read from registers/memory elements and causes execution circuitry that performs convolutions (i.e. first sub-circuit) to perform a convolution operation on the set of input tensors.) or a batch normalization operation using a second sub-circuit of the neural network operation circuitry and the set of data (Lichtenau: Figures 2A, 3C, and 3F-G elements 204, 214, 218, 365, and 388, paragraphs 59-60, 72, 100, 107, 109, and 258-266)(Decoding a NNPA instruction with a batch norm function code causes the input tensors to be read from registers/memory elements and causes the execution circuitry that performs batch normalizations (i.e. second sub-circuit) to perform a batch normalization operation on the set of input tensors.), wherein the first sub-circuit includes a first set of circuitry elements, wherein the second sub-circuit includes a second set of circuitry elements, and wherein the first and second sets of circuitry elements at least partially overlap (Lichtenau: Figures 2A, 2C, 3C, and 3F-G elements 204, 214, 218, 260, 365, and 388, paragraphs 59-60, 64-65, 72, 100, 107, 109, 258-266, 327-328, and 334-335)(A batch normalization operation uses at least register circuitry, memory circuitry, multiplication circuitry, accumulation circuitry, and rounding circuitry. A convolution operation uses at least register circuitry, memory circuitry, multiplication circuitry, and accumulation circuitry. The circuitry overlaps in one of at least the register, memory, multiplication, and/or accumulation.), and
wherein the decoder circuitry is configured to cause the first sub-circuit to perform the convolution operation on the set of data at a same numerical precision or at different numerical precisions (Lichtenau: Figures 2A, 2C, 3C, 3F-G, and 4 elements 204, 214, 218, 260, 365, 384, 388, and 400-406, paragraphs 59-60, 64-65, 72, 100, 103, 107, 109, 121-125, 327-328, and 334-335)(Decoding a NNPA instruction with a convolution function code causes the input tensors to be read from registers/memory elements and causes execution circuitry that performs convolutions (i.e. first sub-circuit) to perform a convolution operation on the set of input tensors. The data type within the tensor descriptor allows for operating on 16-bit floating point elements (i.e. performs convolution operation at same precision).).
As per claim 2:
Lichtenau disclosed the processing device of claim 1, wherein the neural network instruction specifies the set of data by specifying register operands (Lichtenau: Figures 1B, 3B, 3D, and 3F-3G elements 158-160, 320, 365, and 382-388, paragraphs 56, 67-69, 73, 86, 100-101, 103, and 105-107)(The NNPA instruction specifies multiple registers to configure the operation.) and a selector operand (Lichtenau: Figures 2C, 3C, and 3F-3G elements 365 and 382-388, paragraphs 64-65, 86, 100-101, 103, 105-107, 258-266, and 327-335)(The broadest reasonable interpretation of selector operand in view of the specification are enable values for enabling batch normalization. Both the NNPA convolution and batch norm instructions are configured to specify inputs for enabling batch normalization processing.).
As per claim 5:
Lichtenau disclosed the processing device of claim 2, wherein the selector operand specifies a first value based on the operation being the convolution operation and a second value based on the operation being the batch normalization operation (Lichtenau: Figures 2C, 3C, and 3F-3G elements 365 and 382-388, paragraphs 64-65, 86, 100-101, 103, 105-107, 258-266, and 327-335)(The broadest reasonable interpretation of selector operand in view of the specification are enable values for enabling batch normalization. Both the NNPA convolution and batch norm instructions are configured to specify inputs for enabling batch normalization processing.).
As per claim 9:
Claim 9 essentially recites the same limitations of claim 1. Therefore, claim 9 is rejected for the same reasons as claim 1.
As per claim 10:
The additional limitation(s) of claim 10 basically recite the additional limitation(s) of claim 1. Therefore, claim 10 is rejected for the same reason(s) as claim 1.
As per claim 11:
The additional limitation(s) of claim 11 basically recite the additional limitation(s) of claim 2. Therefore, claim 11 is rejected for the same reason(s) as claim 2.
As per claim 17:
Claim 17 essentially recites the same limitations of claim 1. Therefore, claim 17 is rejected for the same reasons as claim 1.
As per claim 18:
The additional limitation(s) of claim 18 basically recite the additional limitation(s) of claim 2. Therefore, claim 18 is rejected for the same reason(s) as claim 2.
New Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4, 6-8, 12-16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lichtenau et al. (U.S. 2022/0405556), in view of Official Notice
As per claim 3:
Lichtenau disclosed the processing device of claim 2, wherein:
the register operands correspond to register locations (Lichtenau: Figures 1B, 3B, 3D, and 3F-3G elements 158-160, 320, 365, and 382-388, paragraphs 56, 67-69, 73, 86, 100-101, 103, and 105-107)(The NNPA instruction specifies multiple registers to configure the operation.); and
the register locations comprise locations for input data registers, weight data registers, and destination data registers (Lichtenau: Figures 3D and 3F-3G elements 320, 365, and 382-388, paragraphs 73, 86, 100-101, 103, and 105-107)(The NNPA instruction specifies multiple input tensors, including input features and weights, as well as specifying output tensors. Official notice is given that source and destination matrices can be stored in registers for the advantage of faster access times. Thus, it would have been obvious to one of ordinary skill in the art to implement storing source and destination matrices in Lichtenau within registers.).
As per claim 4:
Lichtenau disclosed the processing device of claim 3, wherein the decoder circuitry is further configured to:
provide a first set of register locations to the neural network operation circuitry based on the neural network instruction specifying the convolution operation (Lichtenau: Figures 2A, 2C, 3C-D, and 3F-3G elements 204, 214, 218, 260, 320, 365, and 382-388, paragraphs 59-60, 64-65, 72-73, 86, 100-101, 103, 105-107, 327-328, and 334-335)(Decoding a NNPA instruction with a convolution function code causes the execution circuitry that performs convolutions to perform a convolution operation on the set of input tensors and write to the output tensor location. In view of the above official notice, the source and destination tensors are stored in registers.); and
provide a second set of register locations to the neural network operation circuitry based on the neural network instruction specifying the batch normalization operation (Lichtenau: Figures 2A, 3C-D, and 3F-3G elements 204, 214, 218, 320, 365, and 382-388, paragraphs 59-60, 72-73, 86, 100-101, 103, 105-107, and 258-266)(Decoding a NNPA instruction with a batch norm function code causes the execution circuitry that performs batch normalization to perform a batch normalization operation on the set of input tensors and write to the output tensor location. In view of the above official notice, the source and destination tensors are stored in registers.).
As per claim 6:
Lichtenau disclosed the processing device of claim 1, wherein the decoder circuitry is configured to cause the neural network operation circuitry to perform the convolution operation using the first sub-circuit of the neural network operation circuitry in a single cycle (Lichtenau: Figures 2A, 2C, and 3C elements 204, 214, 218, and 260, paragraphs 59-60, 64-65, 72, 327-328, and 334-335)(Decoding a NNPA instruction with a convolution function code causes the execution circuitry that performs convolutions (i.e. first sub-circuit) to perform a convolution operation on the set of input tensors. Lichtenau doesn’t detail how many clock cycle(s) it takes to execute instructions. Official notice is given that instructions can be executed over a single clock cycle for the advantage of increased performance from smaller execution stages. Thus, it would have been obvious to one of ordinary skill in the art to implement instruction execution of the convolution instruction over a single clock cycle.).
As per claim 7:
Lichtenau disclosed the processing device of claim 1, wherein the decoder circuitry is configured to cause the neural network operation circuitry to perform the batch normalization operation using the second sub-circuit of the neural network operation circuitry in two cycles (Lichtenau: Figures 2A and 3C elements 204, 214, and 218, paragraphs 59-60, 72, and 258-266)(Decoding a NNPA instruction with a batch norm function code causes the execution circuitry that performs batch normalization (i.e. second sub-circuit) to perform a batch normalization operation on the set of input tensors. Lichtenau doesn’t detail how many clock cycle(s) it takes to execute instructions. Official notice is given that multiply-accumulate instructions can be executed over many clock cycles, including two, for the advantage of increased performance from lengthening clock frequencies. Thus, it would have been obvious to one of ordinary skill in the art to implement instruction execution of the batch norm instruction over two clock cycles by separating multiplication and accumulation in different clock cycles.), wherein to cause the neural network operation circuitry to perform the batch normalization operation in the two cycles, the decoder circuitry is configured to:
during a first cycle of the two cycles, enable a first subset of circuitry elements of the second set of circuitry elements and capture first output values using a storage circuit of the first subset of circuitry elements (Lichtenau: Figures 2A and 3C elements 204, 214, and 218, paragraphs 59-60, 72, and 258-266)(Decoding a NNPA instruction with a batch norm function code causes the execution circuitry that performs batch normalization (i.e. second sub-circuit) to perform a batch normalization operation on the set of input tensors. Lichtenau doesn’t detail how many clock cycle(s) it takes to execute instructions. In view of the above official notice, the product calculation is performed in a first clock cycle. Official notice is given that intermediate execution results can be stored temporarily for the advantage of quickly accessing intermediate results for further processing. Thus, it would have been obvious to one of ordinary skill in the art to store the product calculation in temporary storage.); and
during a second cycle of the two cycles, enable a second subset of circuitry elements of the second set of circuitry elements, including at least some of the circuitry elements of the first subset of circuitry elements, and capture final output values for the batch normalization operation based on the first output values (Lichtenau: Figures 2A and 3C elements 204, 214, and 218, paragraphs 59-60, 72, and 258-266)(Decoding a NNPA instruction with a batch norm function code causes the execution circuitry that performs batch normalization (i.e. second sub-circuit) to perform a batch normalization operation on the set of input tensors. Lichtenau doesn’t detail how many clock cycle(s) it takes to execute instructions. In view of the above official notice, the accumulation and rounding calculation is performed in a second clock cycle. In view of the above official notice, the product is accessed from temporary storage (e.g. first subset of circuitry elements) to accumulate with a third tensor.).
As per claim 8:
Lichtenau disclosed the processing device of claim 1, wherein the neural network operation circuitry comprises multiplexers (Lichtenau: Figure 1B element 152, paragraph 56)(Official notice is given that multiplexers can be used in operand fetching from registers for the advantage of selecting the required register needed for an instruction. Thus, it would have been obvious to one of ordinary skill in the art to implement multiplexers in Lichtenau.), multiplier circuits (Lichtenau: Figure 2C element 260, paragraphs 64-65), adder circuits (Lichtenau: Figure 2C element 260, paragraphs 64-65), shifter circuits, sign addition circuits (Lichtenau: Figure 1B element 154, paragraph 56)(Official notice is given that instructions can be implemented to perform shift and signed addition operations for the advantage of performing faster division operations and performing addition operations on positive/negative values. Thus, it would have been obvious to one of ordinary skill in the art to implement both shifting and signed addition circuitry in Lichtenau.), and clamp circuits (Lichtenau: Figure 2C element 260, paragraphs 64-65, 327-328, and 334-335)(The activation function performs a clipping function (i.e. clamp) that ensures values don’t exceed a threshold value.), wherein the first sub-circuit of the neural network operation circuitry comprises:
a first subset of the multiplexers (Lichtenau: Figures 2A, 2C, 3C, and 3F-G elements 204, 214, 218, 260, 365, and 388, paragraphs 59-60, 64-65, 72, 100, 107, 109, 327-328, and 334-335)(Decoding a NNPA instruction with a convolution function code causes the input tensors to be read from registers/memory elements and causes execution circuitry that performs convolutions (i.e. first sub-circuit) to perform a convolution operation on the set of input tensors. In view of the above official notice, multiplexers are used in accessing registers for the NNPA instruction.),
a first subset of the multiplier circuits (Lichtenau: Figures 2A, 2C, 3C, and 3F-G elements 204, 214, 218, 260, 365, and 388, paragraphs 59-60, 64-65, 72, 100, 107, 109, 327-328, and 334-335)(Decoding a NNPA instruction with a convolution function code causes the input tensors to be read from registers/memory elements and causes execution circuitry that performs convolutions (i.e. first sub-circuit) to perform a convolution operation on the set of input tensors. The circuitry to perform the product calculation for the convolution function reads upon the first subset of multiplier circuits.),
a first subset of the adder circuits (Lichtenau: Figures 2A, 2C, 3C, and 3F-G elements 204, 214, 218, 260, 365, and 388, paragraphs 59-60, 64-65, 72, 100, 107, 109, 327-328, and 334-335)(Decoding a NNPA instruction with a convolution function code causes the input tensors to be read from registers/memory elements and causes execution circuitry that performs convolutions (i.e. first sub-circuit) to perform a convolution operation on the set of input tensors. The circuitry to perform the accumulation reads upon the first subset of adder circuits.),
a first subset of the shifter circuits (Lichtenau: Figure 1B element 154, paragraph 56)(In view of the above official notice, circuitry is included to perform shift operations.), and
a first subset of the sign addition circuits (Lichtenau: Figure 1B element 154, paragraph 56)(In view of the above official notice, circuitry is included to perform signed addition operations.); and
wherein the second sub-circuit of the neural network operation circuitry comprises:
a second subset of the multiplexers including the first subset of multiplexers (Lichtenau: Figures 2A, 3C, and 3F-G elements 204, 214, 218, 365, and 388, paragraphs 59-60, 72, 100, 107, 109, and 258-266)(Decoding a NNPA instruction with a batch norm function code causes the input tensors to be read from registers/memory elements and causes the execution circuitry that performs batch normalization (i.e. second sub-circuit) to perform a batch normalization operation on the set of input tensors. In view of the above official notice, multiplexers are used in accessing registers for the NNPA instruction.),
the first set of multiplier circuits (Lichtenau: Figures 2A, 3C, and 3F-G elements 204, 214, 218, 365, and 388, paragraphs 59-60, 72, 100, 107, 109, and 258-266)(Decoding a NNPA instruction with a batch norm function code causes the input tensors to be read from registers/memory elements and causes the execution circuitry that performs batch normalization (i.e. second sub-circuit) to perform a batch normalization operation on the set of input tensors. The circuitry to perform the product calculation for the batch norm function reads upon the first subset of multiplier circuits),
the first set of adder circuits (Lichtenau: Figures 2A, 3C, and 3F-G elements 204, 214, 218, 365, and 388, paragraphs 59-60, 72, 100, 107, 109, and 258-266)(Decoding a NNPA instruction with a batch norm function code causes the input tensors to be read from registers/memory elements and causes the execution circuitry that performs batch normalization (i.e. second sub-circuit) to perform a batch normalization operation on the set of input tensors. The circuitry to perform the accumulation reads upon the first subset of adder circuits.),
a second set of shifter circuits including the first set of shifter circuits a first subset of the shifter circuits (Lichtenau: Figure 1B element 154, paragraph 56)(In view of the above official notice, circuitry is included to perform shift operations.),
the first set of sign addition circuits (Lichtenau: Figure 1B element 154, paragraph 56)(In view of the above official notice, circuitry is included to perform signed addition operations.); and
the clamp circuits (Lichtenau: Figure 2C element 260, paragraphs 64-65, 327-328, and 334-335)(The activation function performs a clipping function (i.e. clamp) that ensures values don’t exceed a threshold value.), and
a storage circuit (Lichtenau: Figures 2A and 3C elements 204, 214, and 218, paragraphs 59-60, 72, and 258-266)(Decoding a NNPA instruction with a batch norm function code causes the execution circuitry that performs batch normalization (i.e. second sub-circuit) to perform a batch normalization operation on the set of input tensors. Official notice is given that intermediate execution results can be stored temporarily for the advantage of quickly accessing intermediate results for further processing. Thus, it would have been obvious to one of ordinary skill in the art to store the product calculation in temporary storage (i.e. storage circuit).).
As per claim 12:
The additional limitation(s) of claim 12 basically recite the additional limitation(s) of claims 3 and 5. Therefore, claim 12 is rejected for the same reason(s) as claims 3 and 5.
As per claim 13:
Lichtenau disclosed the apparatus of claim 12, wherein, when the neural network instruction specifies the convolution operation, the decoder circuitry is configured to cause the first sub-circuit of the neural network operation circuitry to perform the convolution operation using a first subset of the set of values (Lichtenau: Figures 2A, 2C, and 3C elements 204, 214, 218, and 260, paragraphs 59-60, 64-65, 72, 327-328, and 334-335)(Decoding a NNPA instruction with a convolution function code causes the execution circuitry that performs convolutions (i.e. first sub-circuit) to perform a convolution operation on the set of input tensors. A subset can equal the whole input tensor. Additionally, official notice is given that input tensors/matrices can include zero values that are ignored by the processing circuits for the advantage of reducing power usage from multiplications by zero. Thus, it would have been obvious to one of ordinary skill in the art to send a partial subset of non-zero values to the convolution circuit for multiplication.).
As per claim 14:
Lichtenau disclosed the apparatus of claim 13, wherein to cause the first sub-circuit of the neural network operation circuitry to perform the convolution operation using the first subset of the set of values (Lichtenau: Figures 2A, 2C, and 3C elements 204, 214, 218, and 260, paragraphs 59-60, 64-65, 72, 327-328, and 334-335)(Decoding a NNPA instruction with a convolution function code causes the execution circuitry that performs convolutions (i.e. first sub-circuit) to perform a convolution operation on the set of input tensors.), the decoder circuitry is configured to provide a first set of register locations and the first value specified by the selector operand to the first sub-circuit (Lichtenau: Figures 3D and 3F-3G elements 320, 365, and 382-388, paragraphs 73, 86, 100-101, 103, and 105-107)(The NNPA instruction specifies multiple input tensors, including input features and weights, as well as specifying output tensors. In view of the above official notice, the source and destination tensors are stored in registers that are accessed upon decoding the instruction.).
As per claim 15:
Lichtenau disclosed the apparatus of claim 12, wherein, when the neural network instruction specifies the batch normalization circuitry, the decoder circuitry is configured to cause the second sub-circuit of the neural network operation circuitry to perform the batch normalization circuitry using a second subset of the set of values (Lichtenau: Figures 2A and 3C elements 204, 214, and 218, paragraphs 59-60, 72, and 258-266)(Decoding a NNPA instruction with a batch norm function code causes the execution circuitry that performs batch normalization (i.e. second sub-circuit) to perform a batch normalization operation on the set of input tensors. A subset can equal the whole input tensor. Additionally, official notice is given that input tensors/matrices can include zero values that are ignored by the processing circuits for the advantage of reducing power usage from multiplications by zero. Thus, it would have been obvious to one of ordinary skill in the art to send a partial subset of non-zero values to the convolution circuit for multiplication.).
As per claim 16:
Lichtenau disclosed the apparatus of claim 15, wherein to cause the second sub-circuit of the neural network operation circuitry to perform the batch normalization operation using the second subset of the set of values (Lichtenau: Figures 2A and 3C elements 204, 214, and 218, paragraphs 59-60, 72, and 258-266)(Decoding a NNPA instruction with a batch norm function code causes the execution circuitry that performs batch normalization (i.e. second sub-circuit) to perform a batch normalization operation on the set of input tensors.), the decoder circuitry is configured to provide a second set of register locations and the second value specified by the selector operand to the second sub-circuit (Lichtenau: Figures 3D and 3F-3G elements 320, 365, and 382-388, paragraphs 73, 86, 100-101, 103, and 105-107)(The NNPA instruction specifies multiple input tensors, including input features and weights, as well as specifying output tensors. In view of the above official notice, the source and destination tensors are stored in registers that are accessed upon decoding the instruction. In view of the above official notice, the source and destination tensors are stored in registers that are accessed upon decoding the instruction.).
As per claim 19:
The additional limitation(s) of claim 19 basically recite the additional limitation(s) of claims 3 and 5. Therefore, claim 19 is rejected for the same reason(s) as claims 3 and 5.
As per claim 20:
The additional limitation(s) of claim 20 basically recite the additional limitation(s) of claims 6-7. Therefore, claim 20 is rejected for the same reason(s) as claims 6-7.
Response to Arguments
The arguments presented by Applicant in the response, received on 3/2/2026 are not considered persuasive.
Applicant argues regarding claims 1, 9, and 17:
“In contrast with the teachings of Lichtenau, the Applicant respectfully submits that amended claim 1 recites, in part, that "the decoder circuitry is configured to cause the first sub- circuit to perform the convolution operation on the set of data at a same numerical precision or at different numerical precisions." By way of Example, the Applicant's neural network operation circuitry includes various circuity elements that can be selectively enabled or disabled based on the decoder's instructions, resulting in the performance of 8-bit by 8-bit convolution operations or 16-bit by 8-bit convolution operations (e.g., See Applicant's Specification, at Para. [0066]). The Applicant respectfully asserts that Lichtenau fails to teach or suggest claim 1 as amended herein. More particularly, Lichtenau, while disclosing convolution operations, fails to teach or suggest convolution circuitry that is instruction-configurable to operate in different numerical precision modes. At most, Lichtenau describes that tensors or parameters may be represented using a particular bit width. Such disclosure relates to data representation, however, not to hardware configuration to selectively enable different modes, resulting in different convolution outputs. As such, claim 1 is allowable over the cited art and such indication is respectively requested.”
This argument is not found to be persuasive for the following reason. The encoding of NNPA instructions allows for specifying a data type, as shown by elements 384 and 400-406 in figures 3G and 4. Lichtenau describes in paragraphs 103 and 121-125 that the data type used for operations are 16-bit floating point elements. This allows for a NNPA instruction with a convolution function to perform a convolution operation on 16-bit floating-point elements of source input and weight tensors. Thus, reading upon the newly claimed limitation.
Conclusion
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183
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