DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/23/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
5. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character:
- Fig. 1, reference character “102” has been used to designate both “IC” and “VBAT”. As recited in p. 0018 line 1 “Voltage source 102 is coupled to the input voltage terminal 110.”, it seems that reference character “102” corresponds to the voltage source.
- Fig. 6, reference character “606” has been used to designate both transistor “Mp” and resistor “RPESR”. As recited in p. 0059 lines 4 - 5 recites “FET MP 606 is coupled between...” and p. 0061 lines 4 - 5 recites “That mirrored current flows through the terminal connecting high-voltage capacitor C1 610 and resistor RPESR 608 …”, it seems that reference character 606 corresponds to transistor Mp and reference character 608 corresponds to resistor RPESR.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
6. The disclosure is objected to because of the following informalities:
P. 0022 lines 3 - 4 recites “Having a low IQ can an important requirement for many LDO linear voltage regulators,…”. However, it appears that it should recite “Having a low IQ is an important requirement for many LDO linear voltage regulators,…”.
P.0039 line 4 recites “352at the gate of FET Mn 334…”. However, it appears that it should recite “352 at the gate of FET Mn 334…”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claim 14 is rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US Pub. No. 2009/0128107 A1; (hereinafter Wang et al).
Regarding claim 14, Wang et al [e.g., Fig. 7] discloses a control circuit, comprising: a current source [e.g., current source Ib] having first and second current source terminals [e.g., top and bottom terminals], wherein the first current source terminal is coupled to an input voltage terminal [e.g., current source Ib coupled to VDD rail]; a first transistor [e.g., MP1] having first and second current terminals and a first control terminal [e.g., source, drain and gate], wherein the first current terminal is coupled to the second current source terminal [e.g., top terminal of MP1 coupled to bottom terminal of current source Ib]; a second transistor [e.g., MP2] having third and fourth current terminals and a second control terminal [e.g., drain, source and gate], wherein the third current terminal is coupled to the input voltage terminal [e.g., top terminal of MP2 coupled to VDD rail via current source Ib. Examiner note: For examination purposes, the examiner will interpret the term “coupled” in its broadest sense to refer as electrical components that are connected directly or indirectly in a way that allows for the transfer of electrical energy or signals between them], and the second control terminal is coupled to a feedback terminal [e.g., gate of MP2 coupled to node A]; a first resistor [e.g., Rf1] coupled between an output voltage terminal and the feedback terminal [e.g., coupled between node D and node A]; a second resistor [e.g., Rf2] coupled between the feedback terminal and a ground terminal [e.g., coupled between node A and GND rail]; a third transistor [e.g., MN3] coupled between the second current terminal and the ground terminal [e.g., coupled between bottom terminal of MP1 and GND rail via MN1], and having a third control terminal [e.g., gate]; and a fourth transistor [e.g., MN4] coupled between the fourth current terminal and the ground terminal [e.g., coupled between bottom terminal of MP2 and GND rail via MN2], and having a fourth control terminal coupled to the third control terminal and to the fourth current terminal [e.g., gate of MN4 coupled to gate of MN3 via GND rail and to bottom terminal of MP2 via diode connection (node between R2 and MP2)].
Claim Rejections - 35 USC § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
11. Claim(s) 1, 11 - 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2019/0258282 A1 in view of US. Patent No. 6,765,374 B1; (hereinafter Magod Ramakrishna et al and Yang et al).
Regarding claim 1, Magod Ramakrishna et al [e.g., Fig. 7] discloses a buffer circuit for a linear voltage regulator, comprising: a first transistor [e.g., MN1] having first and second current terminals and a first control terminal [e.g., having drain, source and gate], wherein the first current terminal is coupled to an input voltage terminal [e.g., drain coupled to Vin]; a second transistor [e.g., MNP] having third and fourth current terminals and a second control terminal [e.g., having drain, source and gate], wherein the third current terminal is coupled to the input voltage terminal [e.g., drain coupled to Vin], the fourth current terminal is coupled to an output voltage terminal [e.g., source coupled to Vout], and the second control terminal is coupled to the first control terminal [e.g., gates of MN1 and MNP coupled together]; a third transistor [e.g., MP1] having fifth and sixth current terminals and a third control terminal [e.g., source, drain and gate], wherein the fifth current terminal is coupled to the second current terminal [e.g., source of MP1 coupled to source of MN1]; a fourth transistor [e.g., MP2] having seventh and eighth current terminals and a fourth control terminal [e.g., having source, drain and gate], wherein the seventh current terminal is coupled to the fourth current terminal [e.g., source of MP2 coupled to source MNP], and the fourth control terminal is coupled to the third control terminal and to the eighth current terminal [e.g., gate of MP2 coupled to gate of MP1 and to drain of MP2]; a first current source [e.g., MN2, p. 0050 recites “… current mirror pair MN2 and MN3 ensures equal current flow in both branches, forcing MP1 and MP2 to have the same gate-source voltage (Vgs)…”] coupled between the sixth current terminal and a ground terminal [e.g., coupled between drain of Mp1 and ground]; and a second current source [e.g., MN3, p. 0050 recites “… current mirror pair MN2 and MN3 ensures equal current flow in both branches, forcing MP1 and MP2 to have the same gate-source voltage (Vgs)…”] coupled between the eighth current terminal and the ground terminal [e.g., coupled between drain of MP2 and ground].
Magod Ramakrishna et al does not disclose a resistor coupled between the second current terminal and the fourth current terminal.
Yang et al [e.g., Fig. 2] teaches a resistor [e.g., 100] coupled between the second current terminal and the fourth current terminal [e.g., coupled between the output pass transistor 10 and transistor 45].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Magod Ramakrishna et al with a resistor coupled between the second current terminal and the fourth current terminal as suggested by Yang et al to introduce a stabilizing zero to the transfer function to improve system stability.
Regarding claim 11, Magod Ramakrishna et al [e.g., Fig. 7] discloses wherein the first transistor and the second transistor are each FETs having different areas [e.g. p. 0049 recites “Load-dependent adaptive current is obtained by MN1, which mirrors a fraction (e.g., 1:4000) of the pass transistor (labeled “MNP”) current”], and a ratio of an area of the second transistor to an area of the first transistor is M:1 [e.g., ratio 1:4000].
Regarding claim 12, Magod Ramakrishna et al [e.g., Fig. 7] discloses wherein M is equal to or greater than 100 [e.g., 4000, p. 0049 recites “Load-dependent adaptive current is obtained by MN1, which mirrors a fraction (e.g., 1:4000) of the pass transistor (labeled “MNP”) current”].
Regarding claim 13, Magod Ramakrishna et al discloses the claimed invention except for the wherein the first transistor and the second transistor are each high voltage FETs.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Magod Ramakrishna et al with wherein the first transistor and the second transistor are each high voltage FETs since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Examiner’s Note
12. Examiner has cited particular paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
13. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention
Allowable Subject Matter
14. Claims 2 - 10 and 15 - 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
15. The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 2 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “a fifth transistor having ninth and tenth current terminals and a fifth control terminal, wherein the tenth current terminal is coupled to the sixth current terminal; a sixth transistor having eleventh and twelfth current terminals and a sixth control terminal, wherein the eleventh current terminal is coupled to the input voltage terminal, the twelfth current terminal is coupled to the first control terminal, and the sixth control terminal is coupled to the ninth current terminal; and a third current source coupled between the twelfth current terminal and the ground terminal.”
The primary reason for the indication of the allowability of claim 3 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “a fourth current source having first and second current source terminals, wherein the first current source terminal is coupled to the input voltage terminal; a seventh transistor having thirteenth and fourteenth current terminals and a seventh control terminal, wherein the thirteenth current terminal is coupled to the second current source terminal, and the fourteenth current terminal is coupled to the sixth current terminal; an eighth transistor having fifteenth and sixteenth current terminals and an eighth control terminal, wherein the fifteenth current terminal is coupled to the second current source terminal, and the eighth control terminal is coupled to a feedback terminal; a ninth transistor coupled between the fourteenth current terminal and the ground terminal, and having a ninth control terminal coupled to the sixteenth current terminal; and a tenth transistor coupled between the sixteenth current terminal and the ground terminal, and having a tenth control terminal coupled to the ninth control terminal and to the sixteenth current terminal”.
The primary reason for the indication of the allowability of claim 15 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the current source is a first current source, and the control circuit is further comprising: a fifth transistor having fifth and sixth current terminals and a fifth control terminal, wherein the sixth current terminal is coupled to the second current terminal; a sixth transistor having seventh and eighth current terminals and a sixth control terminal, wherein the seventh current terminal is coupled to the input voltage terminal, and the sixth control terminal is coupled to the fifth current terminal; a second current source coupled between the eighth current terminal and the ground terminal; and a seventh transistor coupled between the input voltage terminal and the output voltage terminal, and having a seventh control terminal coupled to the eighth current terminal”.
Conclusion
16. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US Pub. No. US Pub. No. 2010/0052635 A1 discloses a PMOS LDO linear voltage regulators, more particularly to such LDO voltage regulators having very low quiescent current and good phase margin despite large variations in the load and the output capacitance.
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/ULARISLAO CORDOVA/Examiner, Art Unit 2838
/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838