DETAILED ACTION
1. This Office action is in response to the amendment filed on 04/16/2026
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Drawings
4. Figures 2, 5 and 6 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim(s) 14 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Kronmueller et al (US Pub. No. 2016/0018834 A1); (hereinafter Kronmueller et al).
Regarding claim 14, Kronmueller et al [e.g., Fig. 2] discloses a control circuit, comprising: a current source [e.g., transistor P29 acting as a current source, p. 0036 recites “…, similar to transistor P29 254 which acts as a current source for the differential amplification stage 101.”] having first and second current source terminals [e.g., top and bottom terminals], wherein the first current source terminal is coupled to an input voltage terminal [e.g., transistor P29 coupled to input terminal, Examiner note: For examination purposes, the examiner will interpret the term "coupled" in its broadest sense to refer as electrical components that are connected directly or indirectly in a way that allows for the transfer of electrical energy or signals between them]; a first transistor [e.g., transistor P8] having first and second current terminals and a first control terminal [e.g., source, drain and gate], wherein the first current terminal is coupled to the second current source terminal [e.g., top terminal of transistor P8 coupled to bottom terminal of P29]; a second transistor [e.g., transistor P9] having third and fourth current terminals and a second control terminal [e.g., drain, source and gate], wherein the third current terminal is coupled to the input voltage terminal [e.g., top terminal of transistor P9 coupled to input rail via current source P29], and the second control terminal is coupled to a feedback terminal [e.g., gate of transistor P9 coupled to node between resistors R0 and R1]; a first resistor [e.g., R0] coupled between an output voltage terminal and the feedback terminal [e.g., coupled between output and feedback node]; a second resistor [e.g., R1] coupled between the feedback terminal and a ground terminal [e.g., coupled between feedback node and bottom rail]; a third transistor [e.g., transistor N10] coupled between the second current terminal and the ground terminal [e.g., coupled between bottom terminal of transistor P8 and bottom rail], and having a third control terminal [e.g., gate]; and a fourth transistor [e.g., transistor N9] coupled between the fourth current terminal and the ground terminal [e.g., coupled between bottom terminal of transistor P9 and bottom rail], and having a fourth control terminal electrically shorted to the third control terminal and to the fourth current terminal [e.g., gate of transistor N9 electrically shorted to gate of transistor N10 and top terminal of N9].
Examiner’s Note
7. Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
8. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
9. Applicant’s arguments with respect to claim(s) 14 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
10. Claims 1 - 13 are allowed.
11. Claims 15 - 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 1 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “..; a fifth transistor coupled between the input voltage terminal and the sixth current terminal; a first current source coupled between the sixth current terminal and a ground terminal; and a second current source coupled between the eighth current terminal and the ground terminal.”
The primary reason for the indication of the allowability of claim 15 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…a sixth transistor having seventh and eighth current terminals and a sixth control terminal, wherein the seventh current terminal is coupled to the input voltage terminal, and the sixth control terminal is coupled to the fifth current terminal; a second current source coupled between the eighth current terminal and the ground terminal; and a seventh transistor coupled between the input voltage terminal and the output voltage terminal, and having a seventh control terminal coupled to the eighth current terminal.”
Conclusion
12. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US Pub. No. 2022/0075402 A1 (Wang et al) discloses a voltage regulator circuit to improve the response time to changes in load current.
US Pub. No. 2009/0128107 A1 (Wang et al) discloses an LDO voltage regulator designed to completely cancel an intermediate gain stage while decreasing a quiescent current.
US Pub. No. 2024/0361793 A1 (Huang et al) discloses a linear regulator includes a pass element, an error amplifier, and a miller compensation circuit.
13. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ULARISLAO CORDOVA whose telephone number is (571)272-4690. The examiner can normally be reached Monday-Friday 7:30 - 5:00 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ULARISLAO CORDOVA/Examiner, Art Unit 2838
/JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
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