CTFR 18/643,401 CTFR 86582 DETAIL ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This Office Action is in response to Applicant’s arguments filed on 04/07/2026. Response to Arguments 07-37 AIA Applicant's arguments filed on 04/07/2026 have been fully considered but they are not persuasive, regarding claims 1-15 and 21-26 . 07-38-01 AIA Applicant’s arguments, see Remarks , filed on 04/07/2026 , with respect to claims 16-20 have been fully considered and are persuasive. The 102 Rejections of claims 16-20 has been withdrawn. Applicant mainly argued regarding independent claims 1, 10 and 16 . New independent claim 21 is argued for same reason as claims 1, 10 and 16 . Dependent claims are merely mentioned for depending on their respective independent claims. See, Applicant’s arguments, in Pg. 12-13 under Allowable Subject Matters, New Claims and Conclusion. Therefore, going forward Examiner will only respond to arguments regarding claims 1 and 10, as will be seen in below. In regards to independent claim 1 , Applicant argument(s) is as follows, PNG media_image1.png 732 1169 media_image1.png Greyscale However, respectfully Examiner disagrees with Applicant’s arguments, in regards to independent claim 1. Please, see following mapped out claim 1, under broadest reasonable (BRI) interpretation(s), PNG media_image2.png 701 1373 media_image2.png Greyscale Furthermore, see following excerpt from Zhang, in regards to (a) taught controllers not being integrated (emphasizing on bolded & underlined elements) and (b) taught 1 st -2 nd controller being separated, using isolation barrier (emphasizing on bolded & underlined elements): [Para 0016] Typically, the controller measures an output characteristic (e.g., an output voltage, an output current, or a combination of an output voltage and an output current) of the power converter, and based thereon modifies a duty cycle of power switches of a hard-switched power converter or a switching frequency of the power switches of a resonant power converter. The duty cycle is a ratio represented by a conduction period of a power switch to a switching period thereof. Thus, if a switch conducts for half of the switching period, the duty cycle for the power switch would be 0.5 (or 50%) . Additionally, as voltage or current for systems, such as a microprocessor powered by the power converter, dynamically change (e.g., as a computational load on a load microprocessor changes), the controller is configured to dynamically increase or decrease the duty cycle or the switching frequency of the power switches therein to maintain an output characteristic, such as an output voltage, at a desired value . A controller for a power converter is generally formed as an integrated circuit with conductive pins that are soldered or otherwise electrically bonded to a printed wiring board in an end product . [Para 0021] The power converter further includes feedback circuit 104 that is employed to transmit a sensed output characteristic across the isolation boundary provided by the power transformer T to the controller 102 . Various circuit devices such as an opto-isolator to provide this isolation function are well known in the art and will not be described further herein in the interest of brevity . [Para 0036] FIG. 5 illustrates embodiment power supply controller integrated circuit 500 used to implement an embodiment low power burst mode. Power supply controller integrated circuit 500 has switching signal generator 512 that generates switching signals 520 and 522 , switching signal drivers 514 and 516 that are used to drive switching signals Q.sub.H and Q.sub.L, amplifier 506, and comparators 502, 504, and 508. In alternative embodiments, amplifier 506 may be a comparator. In some embodiments, dead time generation may be implemented within switching signal generator 512. [Para 0037] In an embodiment, power supply controller integrated circuit 500 may be integrated on a single integrated circuit. Alternatively, some or all of the functionality of integrated circuit 500 may be partitioned across a number of integrated circuits or a number of board level discrete components . [Para 0044] In an embodiment, signals Burst On, Burst Off, and Leaving Burst Mode are used to select between the normal operation mode and the burst mode via selection block 630 . For example , switching signal generator 600 may be enabled via selection block 630 when the Leaving Burst Mode and Burst-on signals are high . [Para 0045] VCO 632 generates the variable frequency switching signal during normal operation. In an embodiment, the switching signal of the VCO 632 depends on V.sub.FB. In an embodiment, feedback signal V.sub.FB may be used to control the frequency of VCO 632. During Burst Mode, VCO 632 may be disabled by selection block 630. [Para 0046] FIG. 7 illustrates block diagram of embodiment LLC resonant converter IC 700 . In an embodiment, burst mode control block 702 in control logic block 704 may be implemented using circuitry shown in FIG. 5 and in FIG. 6a . Converter IC 700 may also include … coupled to pin R.sub.Fmin. Therefore, under BRI and Zhang’s above excerpt, indeed Zhang evidently teaches use of more than one controller(s), if required , as Zhang explicitly stated that taught claimed controller(s) “ may be partitioned across a single or number of integrated circuits or a number of board level discrete components ” (i.e., Zhang’s Para 37, 44 and 46). Furthermore, Zhang’s Fig. 1 teaches of two controllers, such as, feedback circuit 104 and controller IC 102. Based on the above Zhang’s teaching, under BRI one in ordinary skill in the art, could have easily interpreted that element within taught IC may have been selected to be on another numbered of IC controller(s), thus establishing 1 st -nth controllers, as required. Its just a simple circuit design choice. Lastly, Applicant also fails to claim any specific detail connection of the secondary winding and output voltage to the claimed 1 st controller (for example three separate independent inputs or use of three separate independent input pins, etc, used by 1 st controller to establish connection with ‘secondary winding, rectifier and output voltage’). Therefore, under BRI using any one of Zhang’s Fig. 1, 5, 6a and 7, Zhang shows having ‘secondary winding, rectifiers D1-2 and output voltage Vout’ being clearly connected to feedback circuit 104 and IC controller’s various elements. Lastly, Zhang also teaches selecting a circuit design choice by using isolation barrier (i.e., Zhang’s Para 21) to sperate out taught 1 st & 2 nd controllers. Thus, one way or another, under BRI Zhang indeed teaches the following features, “ a first controller ( 1 st controller : combined operation of comparison circuit {used as various mode selection block 630 or burst mode control 702, wherein of such control is explained in detail in Fig. 5: using combined operation of ‘502, 504, 506, 508’}, 620, 602, 620, 604 and 606; Para 36-46) coupled to the second winding (sec. w) , a rectifier (D1-2) , and an output of the circuit (for load receiving output Vout) , the first controller (taught 1 st controller) configured to generate a signal ( signal being slow vs. fast switching frequency of QH-L “Sfw of QH-L”, which is claimed as 2 nd signal in claim 10 ) indicating a voltage on the output (Vout) ; and a second controller ( 2 nd controller : 700 except for 702 & 704; Para 42-46) coupled to the first winding (pri. w) and switches (primary-side half bridge switches QH-L) and separated from the first controller (taught 1 st controller) by the isolation barrier (i.e., magnetic isolation between primary & secondary windings of the transformer T)”, as claimed by claim 1. In regards to independent claim 10 , Applicant argument(s) is as follows, PNG media_image3.png 337 1179 media_image3.png Greyscale However, respectfully Examiner disagrees with Applicant’s arguments, in regards to independent claim 10. Furthermore, see above excerpt from Zhang and Examiner’s explanation, in regards to (a) taught controllers not being integrated (emphasizing on bolded & underlined elements) and (b) taught 1 st -2 nd controller being separated, using isolation barrier (emphasizing on bolded & underlined elements), which is also applicable herein for claim 10. For brevity’s sake, Examiner opted out to repeat the rationale here. Next, please, see following mapped out claim 10, under broadest reasonable (BRI) interpretation(s), PNG media_image4.png 602 1385 media_image4.png Greyscale Examiner also fails to see where in claim 10, Applicant claimed any controllers “receiving switching signal (rather Applicant claims of providing switching signal)”, which Applicant argued in above remarks. Applicant also fails to specify what Applicant means by (i) hysteresis band (is it frequency, voltage, current or power consumption bands?), (ii) a second signal (besides having 2 nd signal being combined with 2rd signal, what is this 2 nd signal?), (iii) a third signal indicating status of the circuit (what status- varied switching frequency, duty cycle, detecting fault and/or detecting load condition, etc.?) and (iv) multiple modes. Furthermore, Applicant’s end goal is to maintain output voltage Vcc within a range, during different operational mode, as claimed by each independent claims 1, 10, 16 and 21. For comparing purposes, Examiner is providing Applicant’s original Fig. 8, PNG media_image5.png 640 837 media_image5.png Greyscale Above Fig. 8 from Applicant’s own invention provided to compare with following Zhang’s annotated Fig. 3 and related excerpt PNG media_image6.png 514 956 media_image6.png Greyscale PNG media_image7.png 511 948 media_image7.png Greyscale TABLE I is details of non-overlapping Multiple operation modes: see, Fig. 3; Para 27-35. These modes of operation are performed to not overcharge or undercharge Cout, to maintain output Vout in a steady state, as required by load, thus, preventing in-rush current for the load. These modes of operation are also performed, in response to Sfw of QH-L, which is shown as fixed Sfw of QH-L, wherein QH-L operates in an alternative manner, but varied frequency can be used, see Para 25 last 4 lines and para 45. Therefore, Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time. 1 st controller from the secondary-side operation based on Vout or Vfb comparing : combined operation of 620, 602, 620, 604 and 606 ( wherein for claims 1 & 16 includes following comparison circuit, as well) ; Para 36-46. Comparison circuit “comp” : used as various mode selection block 630 or burst mode control 702, wherein of such control is explained in detail in Fig. 5: using combined operation of ‘502, 504, 506, 508’. Note that comparison circuit comparing output Vout with a) hysteresis band : burst-on threshold 306 Vref 1 low & burst-off threshold 304 Vref3 high to provide 1 st signal ON/OFF signal; and comparison circuit also comparing output Vout with b) deadtime Threshold Vref 2 and exiting burst-mode threshold Vref 4 to provide a 3 rd signal being normal mode or deadtime mode, as feedback side protection circuit. Note that taught 2 nd controller for the primary-side drive control operation to drive: 700 except for 702 & 704; Para 42-46; wherein taught 2 nd controller also includes various protection circuits (i.e., UVLO/short circuit 706, brown out protection 712, soft-start 714, over-current protection 710). MODE 1: during normal mode 322 is a capped, variable duty cycle mode. response to Sfw of QH-L at a steady or fixed frequency; causing to slowly turning on QH-L within a shorter pulse, in alternative manner. MODE 2: during a period, which is between normal mode and low-power burst mode operation 334 is an uncapped, variable duty cycle mode. response to Sfw of QH-L at a slow frequency, prior to reaching 306; causing QH-L with varied longer tuned on pulses. MODE3: during low-power burst mode operation 334, which is within a hysteresis band to maintain the voltage within the hysteresis band mode, response to Sfw of QH-L with faster frequency; causing QH-L being on/off at varied frequency with different controlled or adjusted period of time& repeating cycles; maintaining output Vout within hysteresis band burst-on threshold 306 Vref 1 low & burst-off threshold 304 Vref3 high. MODE 4: after mode 334, but prior to repeat of 322 mode is monitor mode. response to Sfw of QH-L at 0 frequency, in another word; causing both QH=QL=off. Above annotated Fig. 3, excerpt and Table I are from Zhang et al. (“Zhang”, US Pub 2013/0229829) Based on above explanation and Zhang’s Fig. 3, it is also evident that Zhang’s end goal is also to maintain output voltage Vfb (representation of Vout) within a range, during different operational modes, as taught by each independent claims. Thus, one way or another, under BRI Zhang indeed teaches the following features, “ a first controller ( 1 st controller : using taught output of comparison circuit, 620, 602, 620, 604 and 606; Para 36-46) coupled to the voltage comparison circuit (comp) and configured to provide a second signal ( signal being slow vs. fast switching frequency of QH-L “Sfw of QH-L”, which is claimed as 2 nd signal in claim 10 ) combining the first signal (comparison circuit comparing output Vout with a) hysteresis band: burst-on threshold 306 Vref 1 low & burst-off threshold 304 Vref3 high to provide 1 st signal ON/OFF signal) with a third signal (comparison circuit also comparing output Vout with b) deadtime Threshold Vref 2 and exiting burst-mode threshold Vref 4 to provide a 3 rd signal being normal mode or deadtime mode) indicating a status of the circuit (normal mode or deadtime mode) ; and a second controller ( 2 nd controller : 700 except for 702 & 704; Para 42-46) configured to: determine a frequency of a first component of the second signal (Sfw of QH-L frequency being zero vs. slow vs. faster frequency. Note that Fig. 2-4, 6b shows as fixed Sfw of QH-L, wherein QH-L operating in an alternative manner, but varied frequency can be used, see Para 25 last 4 lines and para 45) and operate the switches (QH-L) in one of multiple operation modes (multiple operation modes (see, Fig. 3; Para 27-35), to not overcharge or undercharge Cout, to maintain output Vout in a steady state, as required by load, thus, preventing in-rush current for the load) based on the frequency of the first component (Sfw of QH-L frequency being zero vs. slow vs. faster frequency. Note that Fig. 2-4, 6b shows as fixed Sfw of QH-L, wherein QH-L operating in an alternative manner, but varied frequency can be used, see Para 25 last 4 lines and para 45) ; and when in a first mode of the multiple operation modes, operate the switches (QH-L) based on a frequency of and pulse widths of a second component of the second signal (Sfw of QH-L frequency being zero vs. slow vs. faster frequency. Note that Fig. 2-4, 6b shows as fixed Sfw of QH-L, wherein QH-L operating in an alternative manner, but varied frequency can be used, see Para 25 last 4 lines and para 45)”, as claimed by claim 10. 10. In regards to independent claim 16 , Applicant argument(s) is as follows, PNG media_image8.png 700 1170 media_image8.png Greyscale However, respectfully Examiner disagrees with Applicant’s arguments, in regards to independent claim 16. Furthermore, see above excerpts of Zhang and Examiner’s explanation, in regards to both claims 1 & 10, which is also applicable herein for claim 16. For brevity’s sake, Examiner opted out to repeat the rationale here. Next, please, see following mapped out claim 16, under broadest reasonable (BRI) interpretation(s), PNG media_image9.png 1005 1198 media_image9.png Greyscale Applicant also fails to specify what Applicant means by (i) determine a frequency of a first component, which apparently indicates status of the circuit (what status- varied switching frequency, duty cycle, detecting fault and/or detecting load condition, etc.?), (ii) determine a frequency of a first component of a signal, (iii) the frequency of the first component being at a first level (what level: high, low, zero, slow, fast, normal or sleep/paused, etc.?), (iv) exceed or subject to a cap (what cap: reference, threshold or mode boundaries, etc.?), (v) the frequency of the first component being at a second level (what level: high, low, zero, slow, fast, normal or sleep/paused, etc.?), (vi) the frequency of the first component being at a third level (what level: high, low, zero, slow, fast, normal or sleep/paused, etc.?) and (vii) hysteresis band (is it frequency, voltage, current or power consumption bands?). Based on above explanation and Zhang’s Fig. 3, it is also evident that Zhang’s end goal is also to maintain output voltage Vfb (representation of Vout) within a range, during different operational modes, as taught by each independent claims (same as Applicant’s Fig. 8). Thus, one way or another, under BRI Zhang indeed teaches the following features, “ determine a frequency of a first component of a signal (performing multiple modes of operation, in response to SIGNAL Sfw of QH-L, which is shown as fixed Sfw of QH-L, wherein QH-L operates in an alternative manner, but varied frequency can be used, see Para 25 last 4 lines and para 45. Therefore, Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) in a power converter circuit (DC-DC converter circuit, operating in multiple operation modes (see, Fig. 3; Para 25-35), to not overcharge or undercharge Cout, to maintain output Vout in a steady state, as required by load, thus, preventing in-rush current for the load) , the first component indicating a status of a portion of the power converter circuit; responsive to the frequency of the first component being at a first level ( Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) , operate switches (QH-L, steady vs. shorter vs. longer vs. no duty cycle operation during corresponding mode 1-4, as described in above Fig. 3 & Table I) of the power converter circuit with an increasing duty cycle (when Vout or Vfb is below 306) not to exceed a cap (i.e., not exceeding or being below 306) ; responsive to the frequency of the first component being at a second level ( Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) , operate the switches with an increasing duty cycle (QH-L, steady vs. shorter vs. longer vs. no duty cycle operation during corresponding mode 1-4, as described in above Fig. 3 & Table I) not subject to a cap (when Vout or Vfb is above 306)”, as claimed in claim 16. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 13. Claims 1-5, 10-12, 16-21, 25 are rejected under 102(a)(1) as being anticipated by Zhang et al. (“Zhang”, US Pub 2013/0229829). Regarding independent claim 1 , Zhang teaches (Fig. 1-7; Para 18-47, above annotated Fig.(s) and table I) a circuit (DC-DC converter circuit, operating in multiple operation modes (see, Fig. 3; Para 25-35), to not overcharge or undercharge Cout, to maintain output Vout in a steady state, as required by load, thus, preventing in-rush current for the load) , comprising: a transformer (T;Para 18-26) including first (primary winding “pri. w”) and second (secondary winding “sec. w”) windings forming an isolation barrier (magnetic isolation between primary & secondary windings of the transformer T) ; a first controller ( 1 st controller : combined operation of comparison circuit {used as various mode selection block 630 or burst mode control 702, wherein of such control is explained in detail in Fig. 5: using combined operation of ‘502, 504, 506, 508’}, 620, 602, 620, 604 and 606; Para 36-46) coupled to the second winding (sec. w) , a rectifier (D1-2) , and an output of the circuit (for load receiving output Vout) , the first controller (taught 1 st controller) configured to generate a signal ( signal being slow vs. fast switching frequency of QH-L “Sfw of QH-L”, which is claimed as 2 nd signal in claim 10 ) indicating a voltage on the output (Vout) ; and a second controller ( 2 nd controller : 700 except for 702 & 704; Para 42-46) coupled to the first winding (pri. w) and switches (primary-side half bridge switches QH-L) and separated from the first controller (taught 1 st controller) by the isolation barrier (magnetic isolation between primary & secondary windings of the transformer T) , the second controller (taught 2 nd controller) configured to operate (multiple operation modes (see, Fig. 3; Para 27-35), to not overcharge or undercharge Cout, to maintain output Vout in a steady state, as required by load, thus, preventing in-rush current for the load) the switches (QH-L) to have a capped, variable duty cycle (i.e., see table I) , to have an uncapped, variable duty cycle (i.e., see table I) , or to maintain the voltage within a hysteresis band (see table I) responsive to the signal (Sfw of QH-L frequency being zero vs. slow vs. faster frequency. Note that Fig. 2-4, 6b shows as fixed Sfw of QH-L, wherein QH-L operating in an alternative manner, but varied frequency can be used, see Para 25 last 4 lines and para 45) . Regarding claim 2 , Zhang teaches (Fig. 1-7; Para 18-47, above annotated Fig.(s) and table I) wherein the second controller (taught 2 nd controller) is configured to, upon enablement of the circuit (2 nd controller also includes various protection circuits (i.e., UVLO/short circuit 706, brown out protection 712, soft-start 714, over-current protection 710; Para 42-46) , determine a mode in which to operate the switches (QH-L) based on a frequency of a first component of the signal (Sfw being zero vs. slow vs. faster frequency) . Regarding claim 3 , Zhang teaches (Fig. 1-7; Para 18-47, above annotated Fig.(s) and table I) the second controller (taught 2 nd controller) is configured to operate the switches (QH-L) in a first mode (see, above table I) to have the capped, variable duty cycle responsive to the frequency being at a first level (Sfw being zero vs. slow vs. faster frequency). Regarding claim 4 , Zhang teaches (Fig. 1-7; Para 18-47, above annotated Fig.(s) and table I) wherein the second controller (taught 2 nd controller) is configured to operate the switches (primary-side full bridge switches 222) in a second mode to have the uncapped, variable duty cycle (see, above table I) responsive to the frequency being at a second level (Sfw being zero vs. slow vs. faster frequency) greater than the first level (Sfw at faster frequency with shorter duty cycle period >Sfw at slow slow frequency with longer duty cycle > Sfw at 0 frequency with dead time). Regarding claim 5 , Zhang teaches (Fig. 1-7; Para 18-47, above annotated Fig.(s) and table I) wherein the first controller (taught 1 st controller) is configured to set the frequency at the second level (Sfw at faster frequency with shorter duty cycle period >Sfw at slow slow frequency with longer duty cycle > Sfw at 0 frequency with dead time) responsive to ( Comparison circuit “comp” : used as various mode selection block 630 or burst mode control 702, wherein of such control is explained in detail in Fig. 5: using combined operation of ‘502, 504, 506, 508’. Note that comparison circuit comparing output Vout with a) hysteresis band: burst-on threshold 306 Vref 1 low & burst-off threshold 304 Vref3 high to provide 1 st signal ON/OFF signal; and comparison circuit also comparing output Vout with b) deadtime Threshold Vref 2 and exiting burst-mode threshold Vref 4 to provide a 3 rd signal being normal mode or deadtime mode) the voltage on the output (Vout) exceeding a threshold (comparison circuit also comparing output Vout with b) deadtime Threshold Vref 2 and exiting burst-mode threshold Vref 4 to provide a 3 rd signal being normal mode or deadtime mode) . Regarding independent claim 10 , Zhang teaches (Fig. 1-7; Para 18-47, above annotated Fig.(s) and table I) a circuit (DC-DC converter circuit, operating in multiple operation modes (see, Fig. 3; Para 25-35), to not overcharge or undercharge Cout, to maintain output Vout in a steady state, as required by load, thus, preventing in-rush current for the load) , comprising: switches (primary-side half bridge switches QH-L) coupled to a rectifier (D1-2) and a transformer (magnetic isolation between primary & secondary windings of the transformer T) , the rectifier (D1-2) coupled to an output of the circuit (for load receiving output Vout) ; a voltage comparison circuit ( comparison circuit “comp” : used as various mode selection block 630 or burst mode control 702, wherein of such control is explained in detail in Fig. 5: using combined operation of ‘502, 504, 506, 508’. Note that comparison circuit comparing output Vout with a) hysteresis band: burst-on threshold 306 Vref 1 low & burst-off threshold 304 Vref3 high to provide 1 st signal ON/OFF signal; and comparison circuit also comparing output Vout with b) deadtime Threshold Vref 2 and exiting burst-mode threshold Vref 4 to provide a 3 rd signal being normal mode or deadtime mode) coupled to the output (output Vout) and configured to provide a first signal (comparison circuit comparing output Vout with a) hysteresis band: burst-on threshold 306 Vref 1 low & burst-off threshold 304 Vref3 high to provide 1 st signal ON/OFF signal) indicative of a voltage on the output (Vout) with respect to a hysteresis band (hysteresis band: burst-on threshold 306 Vref 1 low & burst-off threshold 304 Vref3 high) ; a first controller ( 1 st controller : using taught output of comparison circuit, 620, 602, 620, 604 and 606; Para 36-46) coupled to the voltage comparison circuit (comp) and configured to provide a second signal ( signal being slow vs. fast switching frequency of QH-L “Sfw of QH-L”, which is claimed as 2 nd signal in claim 10 ) combining the first signal (comparison circuit comparing output Vout with a) hysteresis band: burst-on threshold 306 Vref 1 low & burst-off threshold 304 Vref3 high to provide 1 st signal ON/OFF signal) with a third signal (comparison circuit also comparing output Vout with b) deadtime Threshold Vref 2 and exiting burst-mode threshold Vref 4 to provide a 3 rd signal being normal mode or deadtime mode) indicating a status of the circuit (normal mode or deadtime mode) ; and a second controller ( 2 nd controller : 700 except for 702 & 704; Para 42-46) configured to: determine a frequency of a first component of the second signal (Sfw of QH-L frequency being zero vs. slow vs. faster frequency. Note that Fig. 2-4, 6b shows as fixed Sfw of QH-L, wherein QH-L operating in an alternative manner, but varied frequency can be used, see Para 25 last 4 lines and para 45) and operate the switches (QH-L) in one of multiple operation modes (multiple operation modes (see, Fig. 3; Para 27-35), to not overcharge or undercharge Cout, to maintain output Vout in a steady state, as required by load, thus, preventing in-rush current for the load) based on the frequency of the first component (Sfw of QH-L frequency being zero vs. slow vs. faster frequency. Note that Fig. 2-4, 6b shows as fixed Sfw of QH-L, wherein QH-L operating in an alternative manner, but varied frequency can be used, see Para 25 last 4 lines and para 45) ; and when in a first mode of the multiple operation modes, operate the switches (QH-L) based on a frequency of and pulse widths of a second component of the second signal (Sfw of QH-L frequency being zero vs. slow vs. faster frequency. Note that Fig. 2-4, 6b shows as fixed Sfw of QH-L, wherein QH-L operating in an alternative manner, but varied frequency can be used, see Para 25 last 4 lines and para 45) . Regarding claim 11 , Zhang teaches (Fig. 1-7; Para 18-47, above annotated Fig.(s) and table I) the multiple operation modes include (i.e., non-overlapping modes 1-4, as explained in above table I; wherein because Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) the first operation mode (mode 1) , a second operation mode (mode 2) , and a third operation mode (mode 3) , and wherein the second controller (taught 2 nd controller) is configured to, responsive to the determination: operate the switches (QH-L) in the first operation mode without first operating the switches in the second or third operation modes (i.e., non-overlapping modes 1-4, as explained in above table I; wherein because Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) , operate the switches (QH-L) in the second operation mode without first operating the switches in the first or third operation modes (i.e., non-overlapping modes 1-4, as explained in above table I; wherein because Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) , and operate the switches (QH-L) in the third operation mode without first operating the switches in the first and second operation modes (i.e., non-overlapping modes 1-4, as explained in above table I; wherein because Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) . Regarding claim 12 , Zhang teaches (Fig. 1-7; Para 18-47, above annotated Fig.(s) and table I) to indicate the status of the circuit, the third signal indicates that the voltage on the output is within the hysteresis band (when normal or deadtime is not triggered) (comparison circuit “comp”: used as various mode selection block 630 or burst mode control 702, wherein of such control is explained in detail in Fig. 5: using combined operation of ‘502, 504, 506, 508’. Note that comparison circuit comparing output Vout with a) hysteresis band: burst-on threshold 306 Vref 1 low & burst-off threshold 304 Vref3 high to provide 1 st signal ON/OFF signal; and comparison circuit also comparing output Vout with b) deadtime Threshold Vref 2 and exiting burst-mode threshold Vref 4 to provide a 3 rd signal being normal mode or deadtime mode) . Regarding independent claim 16 , Zhang teaches (Fig. 1-7; Para 18-47, above annotated Fig.(s) and table I) a computer-readable medium storing instructions which, when executed by a controller (programmable instructions; Para 25) , cause the controller to: determine a frequency of a first component of a signal (performing multiple modes of operation, in response to SIGNAL Sfw of QH-L, which is shown as fixed Sfw of QH-L, wherein QH-L operates in an alternative manner, but varied frequency can be used, see Para 25 last 4 lines and para 45. Therefore, Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) in a power converter circuit (DC-DC converter circuit, operating in multiple operation modes (see, Fig. 3; Para 25-35), to not overcharge or undercharge Cout, to maintain output Vout in a steady state, as required by load, thus, preventing in-rush current for the load) , the first component indicating a status of a portion of the power converter circuit; responsive to the frequency of the first component being at a first level ( Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) , operate switches (QH-L, steady vs. shorter vs. longer vs. no duty cycle operation during corresponding mode 1-4, as described in above Fig. 3 & Table I) of the power converter circuit with an increasing duty cycle (when Vout or Vfb is below 306) not to exceed a cap (i.e., not exceeding or being below 306) ; responsive to the frequency of the first component being at a second level ( Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) , operate the switches with an increasing duty cycle (QH-L, steady vs. shorter vs. longer vs. no duty cycle operation during corresponding mode 1-4, as described in above Fig. 3 & Table I) not subject to a cap (when Vout or Vfb is above 306) ; and responsive to the frequency of the first component being at a third level ( Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) , operate the switches (QH-L, steady vs. shorter vs. longer vs. no duty cycle operation during corresponding mode 1-4, as described in above Fig. 3 & Table I) to maintain a voltage output of the power converter circuit within a hysteresis band (i.e., 334 using taught Comparison circuit “comp”. Note that comparison circuit comparing output Vout with a) hysteresis band: burst-on threshold 306 Vref 1 low & burst-off threshold 304 Vref3 high to provide 1 st signal ON/OFF signal; and comparison circuit also comparing output Vout with b) deadtime Threshold Vref 2 and exiting burst-mode threshold Vref 4 to provide a 3 rd signal being normal mode or deadtime mode, as feedback side protection circuit) and based on a frequency of and pulse widths of a second component of the signal ( Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) . Regarding claim 17 , Zhang teaches (Fig. 1-7; Para 18-47, above annotated Fig.(s) and table I) the instructions cause the controller to turn on the switches (QH-L) responsive to receiving, within a target window of time (i.e., 334 using taught Comparison circuit “comp”. Note that comparison circuit comparing output Vout with a) hysteresis band: burst-on threshold 306 Vref 1 low & burst-off threshold 304 Vref3 high to provide 1 st signal ON/OFF signal) and in the second component of the signal ( Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) , a first pulse and a second pulse wider than the first pulse (i.e., longer duty cycle being 2 nd pulse > shorter duty cycle being 1 st pulse) ( Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) . Regarding claim 18 , Zhang teaches (Fig. 1-7; Para 18-47, above annotated Fig.(s) and table I) the instructions cause the controller to turn off the switches responsive to receiving (i.e., using taught Comparison circuit “comp”. Note that comparison circuit also comparing output Vout with b) deadtime Threshold Vref 2 and exiting burst-mode threshold Vref 4 to provide a 3 rd signal being normal mode or deadtime mode, as feedback side protection circuit) , after the first and second pulses (i.e., longer duty cycle being 2 nd pulse > shorter duty cycle being 1 st pulse) and in the second component of the signal ( Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) , a third pulse wider than the first pulse (i.e., dead-time being required to be longer then repetitive longer vs. shorter alternative on-off duty cycle of QH-L) . Regarding claim 19 , Zhang teaches (Fig. 1-7; Para 18-47, above annotated Fig.(s) and table I) the frequency of the first component being at the second level indicates the absence of a short circuit in the power converter circuit (i.e., using taught 2 nd controller for the primary-side drive control operation to drive: 700 except for 702 & 704; Para 42-46; wherein taught 2 nd controller also includes various protection circuits (i.e., UVLO/short circuit 706, brown out protection 712, soft-start 714, over-current protection 710) ( Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time). Regarding claim 20 , Zhang teaches (Fig. 1-7; Para 18-47, above annotated Fig.(s) and table I) the instructions cause the controller to generate the first component of the signal to have the frequency at the second level responsive to the voltage output exceeding a threshold (i.e., after 306) (i.e., longer duty cycle being 2 nd pulse > shorter duty cycle being 1 st pulse) ( Sfw of QH-L is performed at faster frequency with shorter duty cycle period >Sfw of QH-L is performed at slow frequency with longer duty cycle > Sfw of QH-L is performed at 0 frequency with dead time) . Regarding independent claim 21 , Zhang teaches (Fig. 1-7; Para 18-47, above annotated Fig.(s) and table I) an apparatus, comprising: a first controller ( 1 st controller : combined operation of comparison circuit {used as various mode selection block 630 or burst mode control 702, wherein of such control is explained in detail in Fig. 5: using combined operation of ‘502, 504, 506, 508’}, 620, 602, 620, 604 and 606; Para 36-46) coupled to a rectifier (D1-2) , and an output (for load receiving output Vout) , the first controller configurable to generate a signal including pulses ( signal being slow vs. fast switching frequency of QH-L “Sfw of QH- L” with varied duty cycle, which is claimed as 2 nd signal in claim 10 ) , in which the pulses are separated by a duration (in another word, duty cycle) that reflects a voltage at the output (Vout) ; and a second controller ( 2 nd controller : 700 except for 702 & 704; Para 42-46) coupled to switches (primary-side half bridge switches QH-L) , the second controller being electrically isolated from the first controller by an isolation medium (Para 21 36-37, 46) , the second controller configurable to control a duty cycle of switching of the switches responsive to the signal (i.e., see above annotated Fig. 3 of Zhang & table I, under Response to Arguments) . Regarding claim 25, of 21, further comprising a transformer (T;Para 18-26) including a primary side winding (primary winding “pri. w”) and a secondary side winding (secondary winding “sec. w”) separated by the isolation medium (Para 21 36-37, 46) , wherein the switches (QH, QL) are coupled to the primary side winding of the transformer and the rectifier (d1-2) is coupled to the secondary side winding of the transformer. Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 6-9, 13-15, 22-24 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 6 , cited art(s) failed to teach “ the second controller is configured to operate the switches in a third mode to maintain the voltage within the hysteresis band responsive to the frequency being at a third level greater than the first and second levels (Zhang teaches using 1 st controller to perform the claimed mode of operation, but not 2 nd controller)”. Claims 7-9 are depending from claim 6. Regarding claim 13 , cited art(s) failed to teach “the first controller includes circuitry configured to generate the first signal, the circuitry including: a first pulse generator having a first pulse generator input and a first pulse generator output, the first pulse generator input configured to be triggered by rising pulse edges; a second pulse generator having a second pulse generator input and a second pulse generator output, the second pulse generator input coupled to the first pulse generator output and configured to be triggered by falling pulse edges, the second pulse generator output coupled to an input of an inverter; a third pulse generator having a third pulse generator input and a third pulse generator output, the third pulse generator input coupled configured to be triggered by rising pulse edges; an AND logic gate having an AND logic gate output and first and second AND logic gate inputs, the first AND logic gate input coupled to an output of the inverter, the second AND logic gate input coupled to the first pulse generator input, and the AND logic gate output coupled to the third pulse generator input; a first OR logic gate having a first OR logic gate output and first and second OR logic gate inputs, the first OR logic gate input coupled to the first pulse generator output, the second OR logic gate input coupled to the third pulse generator output; a fourth pulse generator having a fourth pulse generator input and a fourth pulse generator output, the fourth pulse generator input configured to be triggered by falling pulse edges and coupled to the first pulse generator input; and a second OR logic gate having a second OR logic gate output and third and fourth OR logic gate inputs, the third OR logic gate input coupled to the first OR logic gate output, the fourth OR logic gate input coupled to the fourth pulse generator output”. Regarding claim 14 , cited art(s) failed to teach, “the first controller includes circuitry to generate the third signal, the circuitry comprising: a first AND logic gate having a first AND logic gate output and first and second AND logic gate inputs, the second AND logic gate input being an inverting input; a first delay circuit having a first delay circuit output, a first delay circuit input, and a first delay circuit reset input, the first delay circuit reset input being an inverting input and coupled to the first delay circuit input and the first AND logic gate output; and a first pulse generator having a first pulse generator output and a first pulse generator input, the first pulse generator input coupled to the first delay circuit output and triggered by rising pulse edges, the first pulse generator output coupled to the second AND logic gate input”. Regarding claim 15 , cited art(s) failed to teach “the second controller comprises: a two-bit counter having a counter output and first and second counter inputs, the first counter input triggered by rising pulse edges, the second counter input is an enable input; a pulse generator having a pulse generator output and a pulse generator input, the pulse generator input triggered by rising pulse edges and coupled to the first counter input, the pulse generator output coupled to the enable input; a pulse width filter having a pulse width filter output and a pulse width filter input, the pulse width filter input coupled to the pulse generator input; a first AND gate having a first AND gate output and first and second AND gate inputs, the first AND gate input coupled to the counter output, the second AND gate input coupled to the pulse width filter output; a second AND gate having a second AND gate output and third and fourth AND gate inputs, the third AND gate input is an inverting input coupled to the counter output, the fourth AND gate input coupled to the pulse width filter output; and a latch having a latch output and first and second latch inputs, the first latch input coupled to the first AND gate output and the second latch input coupled to the second AND gate output”. Regarding claim 22 , cited art(s) failed to teach, the first controller is configurable to: “ provide the signal having a static first state to the second controller responsive to the voltage being below a first value ; provide the signal having pulses separated by a first duration responsive to the voltage being between the first value and a second value ; and provide the signal having pulses separated by a second duration responsive to the voltage being above the second value ”. Claims 23-24 are depending from claim 22. Regarding claim 26, cited art(s) teaches the transformer is a first transformer, except that the apparatus further comprises “a second transformer including a primary side winding and a secondary side winding separated by the isolation medium, wherein the second controller is coupled to the secondary side winding of the second transformer and the first controller is coupled to the primary side winding of the second transformer, the first controller configurable to transmit the signal to the second controller via the second transformer” . Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NUSRAT QUDDUS whose telephone number is (571)270-7921. The examiner can normally be reached on M-Th 9-4 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CRYSTAL L. HAMMOND can be reached at (571) 270-1682 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NUSRAT QUDDUS/Examiner, Art Unit 2838 /CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838 Application/Control Number: 18/643,401 Page 2 Art Unit: 2838 Application/Control Number: 18/643,401 Page 3 Art Unit: 2838 Application/Control Number: 18/643,401 Page 4 Art Unit: 2838 Application/Control Number: 18/643,401 Page 5 Art Unit: 2838 Application/Control Number: 18/643,401 Page 6 Art Unit: 2838 Application/Control Number: 18/643,401 Page 7 Art Unit: 2838 Application/Control Number: 18/643,401 Page 8 Art Unit: 2838 Application/Control Number: 18/643,401 Page 9 Art Unit: 2838 Application/Control Number: 18/643,401 Page 10 Art Unit: 2838 Application/Control Number: 18/643,401 Page 11 Art Unit: 2838 Application/Control Number: 18/643,401 Page 12 Art Unit: 2838 Application/Control Number: 18/643,401 Page 13 Art Unit: 2838 Application/Control Number: 18/643,401 Page 14 Art Unit: 2838 Application/Control Number: 18/643,401 Page 15 Art Unit: 2838 Application/Control Number: 18/643,401 Page 16 Art Unit: 2838 Application/Control Number: 18/643,401 Page 17 Art Unit: 2838 Application/Control Number: 18/643,401 Page 18 Art Unit: 2838 Application/Control Number: 18/643,401 Page 19 Art Unit: 2838 Application/Control Number: 18/643,401 Page 20 Art Unit: 2838 Application/Control Number: 18/643,401 Page 21 Art Unit: 2838 Application/Control Number: 18/643,401 Page 22 Art Unit: 2838 Application/Control Number: 18/643,401 Page 23 Art Unit: 2838 Application/Control Number: 18/643,401 Page 24 Art Unit: 2838 Application/Control Number: 18/643,401 Page 25 Art Unit: 2838
Prosecution Insights