DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3-9, 11-17, and 19-23 are pending.
Claims 1, 3, 9, 11, 17, and 19 have been amended.
Claims 21-23 are new.
This action is Final.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-6, 8-14, 16-21, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Clavette et al. (hereinafter as Clavette) PGPUB 2021/0120676, and further in view of Gibney et al. (hereinafter as Gibney) USPAT 10,170,994 and Ni PGPUB 2023/0098000.
As per claim 1, Clavette teaches a method for two-stage processor voltage regulation [0037: (a power device module 124 may be a separate power stage of a voltage regulator; thus there are multiple stages of voltage regulation)], the method comprising:
receiving, by a buck switching regulator circuit [0038: (power device module 124 may be a buck converter (buck switching regulator circuit)] formed in an active interposer that is positioned on a module [0037: (power device modules 124 are embedded in the interposer) and 0029: (interposer may be seated in a socket which is attached to a system board (module)], a voltage [0015 and 0021: (power device module 124 convert an intermediate voltage at the power input 120 at the bottom side of the processor interposer to a lower voltage on the top side of the processor interposer)];
outputting, from the buck switching regulator circuit to each of one chip dies positioned on the active interposer based on the received voltage, a first regulated voltage [0023 and 0039: (voltage output of power device module 124 is delivered to processor substrate 108 for providing power to processors (chip dies))];
Clavette does not explicitly teach a plurality of chip dies, generating, by each of one or more on-chip voltage regulators in each of the plurality of chip dies based on the first regulated voltage, a respective second regulated voltage. Clavette does not teach power distribution circuitry details within the processor or processor die.
Gibney teaches an integrated circuit chip/processor die on an interposer that receives an input voltage from a regulator. Gibney is thus similar to Clavette because they both teach processor die on an interposer and the processor die receiving voltage. Gibney further teaches generating, by each of one on-chip voltage regulators in each of the one or more chip dies based on the first regulated voltage, a respective second regulated voltage [FIG. 1, col. 4 lines 33-37, and col. 5 lines 1-57: (voltage regulator 104 provides an output voltage Vout 132 (first regulated voltage) to various LDO voltage regulators on the processor die, and the LDO voltage regulators use the Vout 132 to provide a second regulated voltage output Vout 124-130 to the cores and circuitry elements in the integrated circuit chip)]. Gibney teaches a voltage regulator providing power to an integrated circuit, and providing that power to various LDO voltage regulators on the chip to generate different voltages for different components of the integrated circuit chip.
The combination of Clavette with Gibney leads to the voltage regulator in the interposer in Clavette providing a Vout 132 to the processor die/integrated circuit as in Gibney, and the integrated circuit having various LDO voltage regulators that take the voltage provided from the interposer to generate a second voltage for corresponding components in the integrated circuit as described in Gibney.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Gibney’s teachings a voltage regulator providing voltage to other voltage regulators on the IC chip to generate local output voltages for components on the IC chip in Clavette. Gibney shows the internal circuitry details of each processor chip/die in Clavette. One of ordinary skill in the art would have been motivated to provide local voltage regulators on the processor IC chip to generate voltages for components of the processor IC chip in Clavette because it allows further regulation and customization of voltages for component parts in the IC chip, thereby providing flexibility in voltage generation for component parts of the IC chip and thus protecting the chip from overvoltage or undervoltage scenarios.
Clavette and Gibney do not explicitly teach a plurality of chip dies, generating, by each of one or more on-chip voltage regulators in each of the plurality of chip dies based on the first regulated voltage, a respective second regulated voltage. Although Gibney indicates that the hardware modules can include more than one ASCI chips, Clavette and Gibney shows one die on the interposer instead of a plurality of chip dies.
Ni teaches integrated circuit on an interposer and using voltage regulators to provide power to the circuit. Ni is thus similar to Clavette and Gibney. Ni further teaches a plurality of chip dies positioned on the active interposer [FIG. 11: (a plurality of integrated circuit dies 1103 and 1104 are on top of the interposer 1102)].
The combination of Clavette and Gibney with Ni leads to a plurality of integrated circuit dies being on the interposer where each of the plurality of dies are provided first power by the voltage regulator of Clavette, and each of the plurality of dies use the received first power for various internal LDO regulators to generate second power for circuitry components inside the integrated circuit die. Thus, the combination of the three references would teach generating, by each of one on-chip voltage regulators in each of the one or more chip dies based on the first regulated voltage, a respective second regulated voltage.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Ni’s teachings of placing a plurality of integrated circuit dies on top of the interposer in Clavette and Gibney. Ni shows how hardware modules can have more than one ASIC chip in Clavette and Gibney. One of ordinary skill in the art would have been motivated to place a plurality of integrated circuit dies on top of the interposer in Clavette and Gibney because it allows various circuity chips to be packed closer together and thus saving physical space, which allows for a reduction in size of a computing device.
As per claim 3, Clavette, Gibney, and Ni teach the method of claim 2, wherein each chip die in the plurality of chip dies includes a plurality of on-chip voltage regulators that each receive the first regulated voltage from the buck switching regulator circuit [Gibney FIG. 1: (the integrated circuit/chip die includes a plurality of LDO regulators); claim 3 depends on claim 2 and claim 1 which recites in the alternative language “one or more chip dies” and so the plurality of chip dies limitation is addressed due to the alternative language)].
As per claim 4, Clavette, Gibney, and Ni teach the method of claim 1, wherein each chip die is a processor chip die that includes one or more processor cores [Clavette 0018 and Gibney FIG. 1 core 114)].
As per claim 5, Clavette, Gibney, and Ni teach the method of claim 1, wherein the module is formed on a board [Clavette 0029: (interposer may be seated in a socket which is attached to a system board (module)].
As per claim 6, Clavette, Gibney, and Ni teach the method of claim 5, wherein the voltage received by the buck switching regulator circuit is received from a board voltage regulator positioned on the board that provides the voltage through the board, the module, and the active interposer [Clavette 0017 and 0019: (power converter 104 is positioned on the board and provides voltage to the board, the socket, and the interposer containing the power device module 124)].
As per claim 8, Clavette, Gibney, and Ni teach the method of claim 1, wherein each of the one or more on-chip voltage regulators is a linear regulator circuit [Gibney FIG. 1: (integrated circuit has LDO voltage regulators)].
Claim 9 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
Claim 11 is similar in scope to claim 3 as addressed above and is thus rejected under the same rationale.
Claim 12 is similar in scope to claim 4 as addressed above and is thus rejected under the same rationale.
Claim 13 is similar in scope to claim 5 as addressed above and is thus rejected under the same rationale.
Claim 14 is similar in scope to claim 6 as addressed above and is thus rejected under the same rationale.
Claim 16 is similar in scope to claim 8 as addressed above and is thus rejected under the same rationale.
Claim 17 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
Claim 19 is similar in scope to claim 3 as addressed above and is thus rejected under the same rationale.
Claim 20 is similar in scope to claim 4 as addressed above and is thus rejected under the same rationale.
Claim 21 is similar in scope to claim 6 as addressed above and is thus rejected under the same rationale.
Claim 23 is similar in scope to claim 8 as addressed above and is thus rejected under the same rationale.
Claim(s) 7, 15, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Clavette et al. (hereinafter as Clavette) PGPUB 2021/0120676 in view of Gibney et al. (hereinafter as Gibney) USPAT 10,170,994 and Ni PGPUB 2023/0098000, and further in view of Knight PGPUB 2009/0016090.
As per claim 7, Clavette, Gibney, and Ni teach the method of claim 1.
Clavette, Gibney, and Ni do not teach wherein each of the one or more on-chip voltage regulators is a buck switching regulator circuit. Knight describes using linear regulators rather than buck regulators.
Knight teaches circuitry that uses a voltage regulator. Knight is thus similar to Clavette, Gibney, and Ni. Knight further teaches using a buck switching regulator rather instead of a linear regulator [0022].
The combination of Clavette, Gibney, and Ni with Knight leads to the on-chip voltage regulators being buck switching regulators rather than linear regulators.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Knight’s teachings of using buck switching regulators instead of linear regulators in the integrated circuit chip in Clavette, Gibney, and Ni. One of ordinary skill in the art would have been motivated to substitute linear regulator with buck switching regulator because they are both voltage regulators and there are only a limited types of voltage regulators, and because buck switching regulator can save significant amounts of power and avoid generation of heat when load is less than a maximum expected value [Knight 0022].
Claim 15 is similar in scope to claim 7 as addressed above and is thus rejected under the same rationale.
Claim 22 is similar in scope to claim 7 as addressed above and is thus rejected under the same rationale.
Response to Arguments
Applicant’s arguments, see pages 6-7, filed 1/2/2026, with respect to the rejection(s) of claim(s) 1, 9, and 17 under U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the previously applied prior art in combination with a previously cited prior art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY CHAN whose telephone number is (571)270-5134. The examiner can normally be reached Monday - Friday 10-7 EST.
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/DANNY CHAN/Primary Examiner, Art Unit 2175