Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 5, & 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al., US11404403 (hereinafter referred to as Chung) in view of Liu et al., CN106200180 (hereinafter referred to as Liu).
In regards to claim 1, Chung teaches a display module (display apparatus; [Col. 1, Ln. 30-34]) comprising: a substrate (substrate 70; [Col. 1, Ln. 30-34] & [Fig. 9]); a plurality (tens of thousands to tens of millions; [Col. 1, Ln. 30-34]) of light emitting diode packages (member 81; [Fig. 9]) comprising a plurality (tens of thousands to tens of millions; [Col. 1, Ln. 30-34]) of light emitting diode (micro LEDs; [Col. 1, Ln. 30-34]) at a front surface (top half of member 81; [Fig. 9]) of a plurality of light emitting diode packages and a plurality (quantity of 2; [Fig. 9]) of first electrode pads (pads 52; [Fig. 9]) at a rear surface of the plurality of light emitting diode packages (bottom half of member 81; [Fig. 9]), wherein the plurality of first electrode pads are configured to electrically connect to a plurality (quantity of 2; [Fig. 9]) of second electrode pads (electrode pads 71; [Fig. 9]) at a front surface of the substrate (top of display substrate 70; [Fig. 9]).
Chung does not teach a first electrostatic discharge (ESD) protection wiring provided discontinuously along a first side of the substrate at the front surface of the substrate.
Liu teaches a first electrostatic discharge (ESD) protection wiring (electrostatic discharge protective line; [Abstract]) provided discontinuously (implicit from dotted line; [Fig. 1]) along a first side of the substrate (left vertical side; [Fig. 1]) at the front surface of the substrate (implicit, planar view of the front surface in Fig. 1) (top of substrate 70 in Fig. 5A, Chung).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung in order to incorporate a first electrostatic discharge (ESD) protection wiring provided discontinuously along a first side of the substrate at the front surface of the substrate as taught by Liu. The motivation for doing so would be to implement an ESD protection for a display.
In regards to claim 5, Chung does not teach wherein the first ESD protection wiring is closer to the first side of the substrate than the plurality of first electrode pads.
Liu teaches wherein the first ESD protection wiring is closer to the first side of the substrate than the plurality of first electrode pads (implicit, the traces are closer to the outside edge than the gray zone; [Fig. 1]) (Examiner’s Note: The gray in the center is the LED packages while the esd wiring is the dotted line.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung in order to incorporate wherein the first ESD protection wiring is closer to the first side of the substrate than the plurality of first electrode pads as taught by Liu. The motivation for doing so would be to implement an ESD protection for a display.
In regards to claim 10, Chung teaches a display module (display apparatus; [Col. 1, Ln. 30-34]) comprising: a substrate (substrate 70; [Col. 1, Ln. 30-34] & [Fig. 9]); a plurality (tens of thousands to tens of millions; [Col. 1, Ln. 30-34]) of micro light emitting diode packages (member 81; [Fig. 9]) provided in a grid array (implicit; [Fig. 2]) at a first surface of the substrate (top of display substrate 70; [Fig. 9]).
Chung does not teach a first ESD protection wiring and a second ESD protection wiring which are respectively arranged discontinuously along two sides of the substrate at the first surface of the substrate.
Liu teaches a first ESD protection wiring and a second ESD protection wiring which are respectively arranged discontinuously (implicit by dotted line; [Fig. 1]) along two sides of the substrate at the first surface of the substrate (Examiner’s Note: The first esd wiring would be the one on the left side and the second esd wiring would be the one of the right side of the rectangular lines of the taught esd wiring.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung in order to incorporate a first ESD protection wiring and a second ESD protection wiring which are respectively arranged discontinuously along two sides of the substrate at the first surface of the substrate as taught by Liu. The motivation for doing so would be to implement an ESD protection for a display.
Claim(s) 2-4, 6-8 & 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al., US11404403 (hereinafter referred to as Chung) in view of Liu et al., CN106200180 (hereinafter referred to as Liu) and in further view of Lee et al., US20200350476 (hereinafter referred to as Lee).
In regards to claim 2, Chung & Liu do not teach wherein the front surface of the substrate comprises an insulation layer, and wherein the insulation layer comprises a plurality of first openings which expose the plurality of first electrode pads and a plurality of second openings which expose a portion of the first ESD protection wiring.
Lee teaches wherein the front surface (top of P2-1; [Fig. 7A & 8B]) (top of substrate 70, Chung) of the substrate comprises an insulation layer (third insulating layer 117 as part of P1; [Fig. 7A]), and wherein the insulation layer comprises a plurality of first openings which expose the plurality of first electrode pads (openings of 510 & 530; [Fig. 7A& 8B]) and a plurality of second openings which expose a portion of the first ESD protection wiring (opening of conductive pattern 600; [Fig. 8B]) (Examiner’s Note: The first ESD protection wiring is still the pattern as taught by Liu, which is also in the similar border range as what is taught by Lee. However, Liu’s esd wiring is spaced a little from the edge of the substrate and would create a hole in the insulation layer where the hash portion of the dotted esd wiring is.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung & Liu in order to incorporate wherein the front surface of the substrate comprises an insulation layer, and wherein the insulation layer comprises a plurality of first openings which expose the plurality of first electrode pads and a plurality of second openings which expose a portion of the first ESD protection wiring as taught by Lee. The motivation for doing so would be to provide necessary isolation to control the ESD to within the spark gaps of the discontinuous esd wiring.
In regards to claim 3, Chung & Liu do not teach wherein the first ESD protection wiring comprises: a center part configured to electrically connect to a first electrode pad among the plurality of first electrode pads, and end parts adjacent to other first electrode pads which are spaced apart at both sides of the electrically connected first electrode pad, respectively.
Lee teaches wherein the first ESD protection wiring comprises: a center part configured to electrically connect to a first electrode pad (the esd wiring portion in the center of the substrate electrically connects through a sublayer to the common electrode 530 at the point of 250-1 or 250-2; [] & [Fig. 8B]) among the plurality of first electrode pads (cathode 390 & anode 310; [Fig. 7A]) (pads 52, Chung), and end parts adjacent to other first electrode pads which are spaced apart at both sides of the electrically connected first electrode pad (implicit; [Fig. 8A & 8B]) (Examiner’s Note: The esd wiring as taught by Liu would run somewhere in the middle of the ladder section of the esd wiring 600 as shown in Fig. 8A of Lee. The end parts are the section of the esd wiring on the top end of the substrate.), respectively.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung & Liu in order to incorporate wherein the first ESD protection wiring comprises: a center part configured to electrically connect to a first electrode pad among the plurality of first electrode pads, and end parts adjacent to other first electrode pads which are spaced apart at both sides of the electrically connected first electrode pad, respectively as taught by Lee. The motivation for doing so would be to have proper insulation between the led pads and the esd wirings in order for the esd wirings to operate at the correct voltages.
In regards to claim 4, Chung and Liu do not teach wherein the first ESD protection wiring is configured such that the end parts are exposed by the plurality of second openings.
Lee teaches wherein the first ESD protection wiring is configured such that the end parts are exposed by the plurality of second openings (implicit; [Fig. 7A, 8A & 8B]) (Examiner’s Note: The esd wiring as taught by Liu would run somewhere in the middle of the ladder section of the esd wiring 600 as shown in Fig. 8A of Lee. The first esd wiring would be one on the left side and the second esd wiring would be the one of the right side. Therefore, the openings in the layer 117 on the left side would be the first openings and the one on the right side would be the second openings.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung & Liu in order to incorporate wherein the first ESD protection wiring is configured such that the end parts are exposed by the plurality of second openings as taught by Lee. The motivation for doing so would be to have proper insulation between the LED pads and the esd wirings in order for the esd wirings to operate at the correct voltages.
In regards to claim 6, Chung does not teach wherein the plurality of second openings comprise a line pattern.
Liu teaches wherein the plurality of second openings comprise a line pattern (implicit, the openings would be where the solid line is in the dashed line and therefore, would be a line pattern; [Fig. 1]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung in order to incorporate wherein the plurality of second openings comprise a line pattern as taught by Liu. The motivation for doing so would be to implement an ESD protection for a display.
In regards to claim 7, Chung does not teach the display module of claim 2, further comprising a second ESD protection wiring provided discontinuously along a second side of the substrate, the second side being opposite of the first side of the substrate.
Liu teaches the display module of claim 2, further comprising a second (right vertical side of the dotted line; [Fig. 1]) ESD protection wiring (electrostatic discharge protective line; [Abstract]) provided discontinuously (implicit; [Fig. 1]) along a second side of the substrate (right side of the substrate 1; [Fig. 1]), the second side being opposite of the first side of the substrate (implicit, left is the opposite of right; [Fig. 1]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung in order to incorporate the display module of claim 2, further comprising a second ESD protection wiring provided discontinuously along a second side of the substrate, the second side being opposite of the first side of the substrate as taught by Liu. The motivation for doing so would be to implement an ESD protection for a display.
In regards to claim 8, Chung does not teach wherein the insulation layer further comprises a plurality of third openings which expose end parts of the second ESD protection wiring.
Liu teaches wherein the insulation layer further comprises a plurality of third openings (solid line portions near the corners for the right side of the electrostatic discharge protective line 3; [Fig. 1]) which expose end parts of the second ESD protection wiring (implicit; [Fig. 1]).
[AltContent: arrow][AltContent: arrow][AltContent: textbox (3rd Openings at the ends of the 2nd ESD protection wiring.)][AltContent: rect][AltContent: rect]
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung in order to incorporate wherein the insulation layer further comprises a plurality of third openings which expose end parts of the second ESD protection wiring as taught by Liu. The motivation for doing so would be to implement an ESD protection for a display.
In regards to claim 11, Chung & Liu do not teach wherein the first surface of the substrate comprises an insulation layer, and wherein the insulation layer comprises a plurality of openings which expose a portion of the first ESD protection wiring and a portion of the second ESD protection wiring.
Lee teaches wherein the first surface of the substrate (top of P2-1; [Fig. 7A & 8B]) (top of substrate 70, Chung) comprises an insulation layer (third insulating layer 117 as part of P1; [Fig. 7A]), and wherein the insulation layer comprises a plurality of openings which expose a portion of the first ESD protection wiring and a portion of the second ESD protection wiring (opening of conductive pattern 600; [Fig. 8B]) (Examiner’s Note: The first ESD protection wiring is still the pattern as taught by Liu, which is also in the similar border range as what is taught by Lee. However, Liu’s esd wiring is spaced a little from the edge of the substrate and would create a hole in the insulation layer where the hash portion of the dotted esd wiring is. The first esd wiring would be one on the left side and the second esd wiring would be the one of the right side. Therefore, the openings in the layer 117 on the left side would be the first openings and the one on the right side would be the second openings.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung & Liu in order to incorporate wherein the first surface of the substrate comprises an insulation layer, and wherein the insulation layer comprises a plurality of openings which expose a portion of the first ESD protection wiring and a portion of the second ESD protection wiring as taught by Lee. The motivation for doing so would be to have proper insulation between the LED pads and the esd wirings in order for the esd wirings to operate at the correct voltages.
In regards to claim 12, Chung does not teach wherein the plurality of openings comprise a line pattern.
Liu teaches wherein the plurality of openings comprise a line pattern (implicit, the openings would be where the solid line is in the dashed line and therefore, would be a line pattern; [Fig. 1]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung in order to incorporate wherein the plurality of openings comprise a line pattern as taught by Liu. The motivation for doing so would be to implement an ESD protection for a display.
In regards to claim 13, Chung teaches of a display device (display apparatus 1; [Fig. 1]) comprising: a first substrate (arrangement member 30; [Fig. 1]); a plurality (quantity of 9; [Fig. 1]) of display modules (LED display modules 20-23, ; [Fig. 1]) provided in a grid array (implicit; [Fig. 1]) at the first substrate; and a processor (driver 60; [Fig. 3]) (Examiner’s Note: Liu teaches one driver for each display module. Therefore, the 9 drivers control the plurality of display modules.) configured to control a driving (driving; [Col. 7, Ln. 8-12]) of the plurality of display modules, wherein the plurality of display modules respectively comprise: a second substrate (substrate 70; [Col. 1, Ln. 30-34] & [Fig. 9]); a plurality (tens of thousands to tens of millions; [Col. 1, Ln. 30-34]) of micro light emitting diode packages (member 81; [Fig. 9]) provided in a grid array at a first surface (top of display substrate 70; [Fig. 9]) of the second substrate.
Chung does not teach of the display modules respectively comprise: a first ESD protection wiring and a second ESD protection wiring provided discontinuously along respective sides of the second substrate at the first surface of the second substrate; and an insulation layer which covers the first surface of the second substrate and comprises a plurality of openings which expose a portion of the first ESD protection wiring and a portion of the second ESD protection wiring.
Liu teaches a first ESD protection wiring and a second ESD protection wiring (Examiner’s Note: The first esd wiring would be the one on the left side and the second esd wiring would be the one of the right side of the rectangular lines of the taught esd wiring.) provided discontinuously (implicit by dotted line; [Fig. 1]) along respective sides of the second substrate at the first surface of the second substrate (implicit; [Fig. 1 & 9]).
Liu does not teach an insulation layer which covers the first surface of the second substrate and comprises a plurality of openings which expose a portion of the first ESD protection wiring and a portion of the second ESD protection wiring.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung in order to incorporate a first ESD protection wiring and a second ESD protection wiring provided discontinuously along respective sides of the second substrate at the first surface of the second substrate as taught by Liu. The motivation for doing so would be to implement an ESD protection for a display.
Lee teaches an insulation layer (third insulating layer 117 as part of P1; [Fig. 7A]) which covers the first surface of the second substrate (top of P2-1; [Fig. 7A & 8B]) (top of substrate 70, Chung) and comprises a plurality of openings (opening of conductive pattern 600; [Fig. 8B]) which expose a portion of the first ESD protection wiring and a portion of the second ESD protection wiring (Examiner’s Note: The first ESD protection wiring is still the pattern as taught by Liu, which is also in the similar border range as what is taught by Lee. However, Liu’s esd wiring is spaced a little from the edge of the substrate and would create a hole in the insulation layer where the hash portion of the dotted esd wiring is.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung & Liu in order to incorporate an insulation layer which covers the first surface of the second substrate and comprises a plurality of openings which expose a portion of the first ESD protection wiring and a portion of the second ESD protection wiring as taught by Lee. The motivation for doing so would be to provide necessary isolation to control the ESD to within the spark gaps of the discontinuous esd wiring.
In regards to claim 14, Chung does not teach wherein the plurality of openings comprise a line pattern.
Liu teaches wherein the plurality of openings comprise a line pattern (implicit, the openings would be where the solid line is in the dashed line and therefore, would be a line pattern; [Fig. 1]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung in order to incorporate wherein the plurality of openings comprise a line pattern as taught by Liu. The motivation for doing so would be to implement an ESD protection for a display.
In regards to claim 15, Chung teaches wherein the plurality of display modules further comprise, respectively: a plurality of electrode pads provided at the first surface of the second substrate and configured to electrically connect to the plurality of micro light emitting diode packages.
Chung does not teach wherein the first ESD protection wiring is provided between a first side of the second substrate and the plurality of electrode pads, and wherein the second ESD protection wiring is provided between a second side of the second substrate opposite of the first side of the second substrate, and the plurality of electrode pads.
Liu teaches wherein the first ESD protection wiring is provided between (implicit; [Fig. 1]) a first side (left side of substrate; [Fig. 1]) of the second substrate and the plurality of electrode pads (Examiner’s Note: The gray in the center of Fig. 1 is the LED packages which is where the electrode pads of Chung would be located.), and wherein the second ESD protection wiring is provided between (implicit; [Fig. 1]) a second side (right side of substrate; [Fig. 1]) of the second substrate opposite of the first side of the second substrate, and the plurality of electrode pads (Examiner’s Note: The gray in the center of Fig. 1 is the LED packages which is where the electrode pads of Chung would be located.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung in order to incorporate wherein the first ESD protection wiring is provided between a first side of the second substrate and the plurality of electrode pads, and wherein the second ESD protection wiring is provided between a second side of the second substrate opposite of the first side of the second substrate, and the plurality of electrode pads as taught by Liu. The motivation for doing so would be to implement an ESD protection for a display.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al., US11404403 (hereinafter referred to as Chung) in view of Liu et al., CN106200180 (hereinafter referred to as Liu) and in further view of Kim et al., US20210398479 (hereinafter referred to as Kim).
In regards to claim 9, Chung & Liu do not teach wherein the plurality of light emitting diode packages respectively comprise a micro integrated circuit (micro IC) chip configured to control a driving of the plurality of light emitting diodes.
Kim teaches wherein the plurality of light emitting diode packages (first LED chips; [Abstract]) respectively comprise a micro integrated circuit (micro IC) chip (pixel driving integrated circuit 300; [Fig. 1]) configured to control a driving of the plurality of light emitting diodes (driving; [0024]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Chung & Liu in order to incorporate wherein the plurality of light emitting diode packages respectively comprise a micro integrated circuit (micro IC) chip configured to control a driving of the plurality of light emitting diodes as taught by Kim. The motivation for doing so would be to have a fully integrated package for an easier build of the many LED packages.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US8310043B2 is relevant for showing an esd embodiment that has the esd wiring on only 2 opposite sides. US20190385990A1 is relevant for showing a processor controlling a plurality of microLEDs across several display modules.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMANTHA L FAUBERT whose telephone number is (703)756-1311. The examiner can normally be reached Monday - Friday 8AM - 5PM.
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SAMANTHA LYNETTE FAUBERT
Examiner
Art Unit 2836
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838