DETAILED ACTION
This Office action is in response to the application filed on 23 April 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 8 is objected to because of the following informalities: At lines 4-5 of claim 8, “the secondary-side on-time control signal” should be changed to “a secondary-side on-time control signal”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuchipudi et al. (US Patent 11,018,595; “Kuchipudi”).
In re claim 1, Kuchipudi discloses a controller (Figs. 3-4) for use with an isolated power converter (Fig. 3), the controller comprising a primary-side regulator (302, 322) and a secondary-side regulator (330),
the secondary-side regulator comprising a secondary-side regulation signal generation module (circuitry, not shown explicitly, within 330 for providing feedback or PWM signals to the primary side control 302: see col. 5:45-58), which receives a feedback signal of an output voltage of the isolated power converter (Fig. 3: signals to pins VBUS_IN or VBUS_OUT of 330), generates a first control signal (Fig. 3: signal output from “Start-Stop for secondary PWM” pin) and couples the first control signal to the primary-side regulator (Fig. 3: through pulse transformer 346 or Fig. 4: 440),
the primary-side regulator comprising:
a primary-side regulation (PSR) module (Fig. 4: 414, 416, 418, 422, 424, 432), which receives a voltage signal across a winding in the isolated power converter (Fig. 4: circuit 414 receives voltage across auxiliary winding of transformer 406; see col. 6:7-12) and generates a second control signal for controlling a state of the primary-side power transistor (Fig. 4: signal out of PWM Gen. 424), thereby executing a PSR mode;
a follow-up secondary-side regulation (SSR) module (Fig. 4: 428a, 428b), which receives the first control signal (from pulse transformer 440, equivalent to 346 in Fig. 3) and generates a third control signal for controlling the state of the primary-side power transistor (Fig. 4: Start, Stop), thereby executing an SSR mode; and
a regulation switching module (Fig. 4: 420), which receives the first control signal and thereby executes a switching of the primary-side regulator between the PSR mode and the SSR mode (see Fig. 6, steps 606, 608, 610 and see col. 8:22-31: the controller switches between the primary side control and the secondary side control based on the received first control signal from the secondary side).
In re claim 2, Kuchipudi discloses wherein the PSR module receives the voltage signal across two terminals of an auxiliary winding in the isolated power converter (Fig. 3: 322 and Fig. 4: 414 both shown as receiving voltage across aux winding of the transformer), the auxiliary winding is coupled to a primary-side winding in the isolated power converter (see Figs. 3, 4);
In re claim 13, Kuchipudi discloses wherein the follow-up SSR module comprises a second drive generator module (428a or 428b), which receives the first control signal (signal input from pulse transformer 440) and generates the third control signal for controlling a state of the primary-side power transistor (signal out of 428a, 428b, or 426).
In re claim 14, Kuchipudi discloses wherein when the primary-side regulator is in the PSR mode, upon the regulation switching module receiving the first control signal that is valid, the primary-side regulator switches from the PSR mode to the SSR mode (Fig. 6: steps 606, 608; see col. 8:22-31), and
wherein when the primary-side regulator is in the SSR mode, if the regulation switching module does not receive the first control signal that is valid within a predetermined period of time, the primary-side regulator switches from the SSR mode to the PSR mode (Fig. 6: steps 604, 606, and 610; see id.).
In re claim 15, Kuchipudi discloses wherein the PSR module executes the PSR mode, in which the output voltage rises up to a first reference value (see Fig. 6, steps 602, 604 and see col. 8:8-15; the soft-start operation being understood as an operation when the output voltage begins rising from zero), wherein the follow-up SSR module executes the SSR mode, in which the output voltage rises up to a second reference value (Fig. 6, step 606, 608 and see col. 8:21-28: the post-soft-start normal operation being understood to control the output voltage to its nominal value, greater than zero), and wherein the first reference value is not greater than the second reference value (because the output voltage rises during soft-start to reach the nominal value, as explained above).
In re claim 16, Kuchipudi discloses an isolated power converter (Fig. 3), comprising the controller as defined in claim 1 (see citations with respect to claim 1, above).
In re claim 17, Kuchipudi discloses a control method for an isolated power converter (see Figs. 3, 4, 6), the control method comprising:
at a secondary-side regulation signal generation module, receiving a feedback signal of an output voltage of the isolated power converter, generating a first primary-side power transistor control signal and coupling the first control signal to a primary-side regulator (see the citations for the corresponding secondary-side regulation signal generation module limitations within the device as claimed in claim 1, above in this Office action);
at a primary-side regulation (PSR) module, receiving a voltage signal across a winding in the isolated power converter and generating a second primary-side power transistor control signal for controlling a state of the primary-side power transistor, thereby executing a PSR mode (see the citations for the corresponding PSR module limitations within the device as claimed in claim 1, above in this Office action);
at a follow-up secondary-side regulation (SSR) module, receiving the first control signal and generating a third primary-side power transistor control signal for controlling the state of the primary-side power transistor, thereby executing an SSR mode (see the citations for the corresponding follow-up SSR module limitations within the device as claimed in claim 1, above in this Office action);
at a regulation switching module, receiving first control signal and executing a switching of the primary-side regulator between the PSR and SSR modes (see the citations for the corresponding regulation switching module limitations within the device as claimed in claim 1, above in this Office action); and
during startup of the isolated power converter, first executing the PSR mode by the PSR module and then executing a mode switching by the regulation switching module so that the SSR mode is executed by the follow-up SSR module (see Fig. 6: steps 602, 604, 606, 608 and see col. 8: 3-28; the converter starts up using the PSR primary side control until the first control signal is received from the secondary side, and then uses the SSR secondary side control).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kuchipudi in view of Wang et al. (US 2013/0300384; “Wang”).
In re claim 5, Kuchipudi discloses the invention according to claim 1 as explained above, but does not further disclose wherein the secondary-side regulation signal generation module comprises: a second comparator, which compares the feedback signal with a second reference value, outputs a second comparison result and generates the first control signal that provides a turn-on instruction to the primary-side power transistor based on the second comparison result.
Whereas Wang discloses a controller for an isolated power converter (Figs. 2, 4), wherein the secondary-side regulation signal generation module comprises:
a second comparator (Fig. 2: 102), which compares the feedback signal (Fig. 2: Vfb1) with a second reference value (Fig. 2: Vref1), outputs a second comparison result (Fig. 2: Vc) and generates the first control signal (Figs. 2, 4: signal Con provided through isolator to primary side control) that provides a turn-on instruction to the primary-side power transistor based on the second comparison result (see [0019]), in order to provide for a higher efficiency operation of the power converter ([0005]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the converter of Kuchipudi such that the secondary-side regulation signal generation module comprises: a second comparator, which compares the feedback signal with a second reference value, outputs a second comparison result and generates the first control signal that provides a turn-on instruction to the primary-side power transistor based on the second comparison result, as shown by Wang for the purpose of increasing the operational efficiency of the power converter and controller.
In re claim 7, the above combination of Kuchipudi and Wang necessarily further discloses wherein the follow-up SSR module comprises:
a frequency-based on-time control circuit (Wang, Fig. 4: inverter 104), which receives the first control signal (Wang, Figs. 2, 4: signal Con; equivalent to first control signal in Kuchipudi) and outputs a secondary-side on-time control signal (Wang, Fig. 4: output of 104) for controlling an on-time of the primary-side power transistor (Wang, Figs. 2, 4: transistor M1, controlled via Gate signal); and
a second drive generator module (Wang, Fig. 4: circuits 107, 108), which receives the first control signal (Wang, Figs. 2, 4: Con), the secondary-side on-time control signal (Wang, Fig. 4: output of 104) and a primary-side current sample signal (Wang, Figs. 2, 4: Vcs) and outputs the third control signal to the primary-side power transistor (Wang, Fig. 4: output of circuit 108).
In re claim 8, the above combination of Kuchipudi and Wang necessarily further discloses wherein the follow-up SSR module comprises:
a timing circuit (Wang, Fig. 4: inverter 104), which receives the first control signal (Wang, Figs. 2, 4: signal Con; equivalent to first control signal in Kuchipudi) and outputs, if the first control signal instructs to turn on the primary-side power transistor, the secondary-side on-time control signal (Wang, Fig. 4: output of 104) for controlling the on-time of the primary-side power transistor, after the elapse of a predetermined period of time (that is, after a propagation delay of the inverter 104); and
a second drive generator module (Wang, Fig. 4: circuits 107, 108), which receives the first control signal (Wang, Figs. 2, 4: Con) and the secondary-side on-time control signal (Wang, Fig. 4: output of 104) and outputs the third control signal to the primary-side power transistor (Wang, Fig. 4: output of circuit 108).
In re claim 6, Kuchipudi discloses the invention according to claim 1 as explained above, but does not further disclose wherein the secondary-side regulation signal generation module comprises: a second operational amplifier, which amplifies an error between the feedback signal and a second reference value and outputs a secondary-side amplified error signal; and a second frequency control module, which receives the secondary-side amplified error signal and outputs the first control signal that provides a turn-on instruction to the primary-side power transistor.
Whereas Wang discloses a controller for an isolated power converter (Figs. 2, 4), wherein the secondary-side regulation signal generation module comprises: a second operational amplifier (Fig. 2: 102), which amplifies an error between the feedback signal (Fig. 2: Vfb1) and a second reference value (Fig. 2: Vref1) and outputs a secondary-side amplified error signal (Fig. 2: Vc); and a second frequency control module (Fig. 2: 103, M2, 104), which receives the secondary-side amplified error signal (Vc) and outputs the first control signal that provides a turn-on instruction to the primary-side power transistor (Figs. 2, 4: signal Con; equivalent to first control signal in Kuchipudi), in order to provide for a higher efficiency operation of the power converter ([0005]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the converter of Kuchipudi such that the secondary-side regulation signal generation module comprises: a second operational amplifier, which amplifies an error between the feedback signal and a second reference value and outputs a secondary-side amplified error signal; and a second frequency control module, which receives the secondary-side amplified error signal and outputs the first control signal that provides a turn-on instruction to the primary-side power transistor, as shown by Wang for the purpose of increasing the operational efficiency of the power converter and controller.
In re claim 9, the above combination of Kuchipudi and Wang necessarily further discloses wherein the follow-up SSR module comprises:
a frequency-based on-time control circuit (Wang, Fig. 4: inverter 104), which receives the first control signal (Wang, Figs. 2, 4: signal Con; equivalent to first control signal in Kuchipudi) and outputs a secondary-side on-time control signal (Wang, Fig. 4: output of 104) for controlling an on-time of the primary-side power transistor (Wang, Figs. 2, 4: transistor M1, controlled via Gate signal); and
a second drive generator module (Wang, Fig. 4: circuits 107, 108), which receives the first control signal (Wang, Figs. 2, 4: Con), the secondary-side on-time control signal (Wang, Fig. 4: output of 104) and a primary-side current sample signal (Wang, Figs. 2, 4: Vcs) and outputs the third control signal to the primary-side power transistor (Wang, Fig. 4: output of circuit 108).
In re claim 10, the above combination of Kuchipudi and Wang necessarily further discloses wherein the follow-up SSR module comprises:
a timing circuit (Wang, Fig. 4: inverter 104), which receives the first control signal (Wang, Figs. 2, 4: signal Con; equivalent to first control signal in Kuchipudi) and outputs, if the first control signal instructs to turn on the primary-side power transistor, the secondary-side on-time control signal (Wang, Fig. 4: output of 104) for controlling the on-time of the primary-side power transistor, after the elapse of a predetermined period of time (that is, after a propagation delay of the inverter 104); and
a second drive generator module (Wang, Fig. 4: circuits 107, 108), which receives the first control signal (Wang, Figs. 2, 4: Con) and the secondary-side on-time control signal (Wang, Fig. 4: output of 104) and outputs the third control signal to the primary-side power transistor (Wang, Fig. 4: output of circuit 108).
Allowable Subject Matter
Claims 3-4 and 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claims 3-4, the closest prior art in Kuchipudi discloses the invention according to independent claim 1, but does not further disclose the limitations of dependent claim 3, including those of the PSR module comprising a first operational amplifier, which amplifies an error between the output voltage sample signal and a first reference value and outputs a primary-side amplified error signal; a first frequency control module, which receives the primary-side amplified error signal and outputs a primary-side frequency control signal for controlling a switching frequency of the primary-side power transistor; and a turn-off control module, which receives the primary-side amplified error signal and outputs a primary-side on-time control signal for controlling an on-time of the primary-side power transistor.
Further, the prior art does not suggest to modify Kuchipudi to arrive at the claimed solution, because in Kuchipudi the PSR module uses an open-loop oscillator control scheme, and thus to modify this into the circuitry of claim 3 would change the operating principles of the Kuchipudi disclosure.
With respect to claim 11, the closest prior art in Kuchipudi discloses the invention according to independent claim 1, but does not further disclose the further limitations, including those of a timing circuit, which starts a timer based on the turn-on instruction of the primary-side power transistor and outputs, after the elapse of a predetermined period of time, a secondary-side on-time control signal for controlling an on-time of the primary-side power transistor; and a second logic circuit, which generates the first control signal based on the second comparison result and the secondary-side on-time control signal, as recited in claim 11.
That is, while Kuchipudi, as modified by Wang as proposed above in this Office action may disclose an inverter 104 which acts similarly to a timer in that it delays a signal according to its propagation delay, this does not reasonably correspond to the solution in claim 11, in which the timing circuit starts a timer based on the turn-on instruction of the primary-side power transistor and outputs, after the elapse of a predetermined period of time, a secondary-side on-time control signal for controlling an on-time of the primary-side power transistor.
Claim 12 recites substantially similar limitations as those recited in claim 11 as pointed out above. Therefore claim 12 would be allowable for substantially similar reasons, mutatis mutandis, as provided above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2025/0105747 is a related application having at least a common Applicant with the instant application, and which claims a substantially similar invention, however the invention as claimed in the related application notably lacks the feature of a PSR module that receives a voltage signal across a winding in the isolated power converter, as recited in the claims of the instant application.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838