DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 23, 2024 is being considered by the examiner.
Drawings
The drawings were received on April 23, 2024. These drawings are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Steinberg et al. (U.S. Patent 12,699,291, hereinafter referred to as “Steinberg”). Steinberg anticipates claims:
1 and 17. A photonic integrated circuit (PIC) (see figures 1-7) comprising:
an on-chip electro-absorption modulator (EAM) (compact differential traveling wave electro-absorption modulator CD-TWEAM 100 is interpreted as the EAM) integrated into the PIC and having a first electrode (second electrode 106A, anode, is interpreted as the first electrode) and a second electrode (first electrode 106B, cathode, is interpreted as the second electrode), the first electrode and second electrode comprising an anode and a cathode; and
a first biasing network (termination load 208A and biasing element 210A and all electrically connected components are together interpreted as the first biasing network) electrically coupled to the first electrode, the first biasing network providing both termination and biasing to the EAM (see column 11, line 64 – column 12, line 10), the first biasing network comprising: a first inductor formed on the PIC (see column 11, line 64 – column 12, line 10, the biasing element 210A is an inductor).
2. The PIC of claim 1, wherein: the EAM comprises: an active region (103); and at least one waveguide (102).
3. The PIC of claim 2, wherein: the active region comprises indium phosphide; and the at least one waveguide comprises silicon (see column 3, lines 61-65).
4. The PIC of claim 1, wherein: the first inductor is formed lithographically on the PIC (see figure 4, this limitation is a product-by-process limitation that does not further define the structure).
5. The PIC of claim 2, wherein: the PIC comprises a silicon-based substrate (see column 8, lines 36 – 44); and the first inductor is formed in a metallization layer of the PIC (see figures 1-4).
6 and 18. The PIC of claim 1, wherein: the first biasing network further comprises a first resistor (the termination load comprises a resistor providing resistance, see column 11, line 64 – column 12, line 10) electrically coupled in series with the first inductor (see figure 4).
7. The PIC of claim 6, wherein: the first resistor is formed on the PIC (see figure 4).
8. The PIC of claim 1, further comprising: a second biasing network electrically coupled to the second electrode for providing termination and biasing to the EAM, the second biasing network comprising: a second inductor formed on the PIC (see figure 4, the “B” labeled corresponding elements are interpreted as forming the second biasing network in the same fashion as the “A” labeled elements formed the first biasing network).
9 and 19. The PIC of claim 8, wherein: the second biasing network further comprises a second resistor electrically coupled in series with the second inductor (see column 8, lines 36 – 44).
10. The PIC of claim 9, wherein: the second resistor is formed on the PIC (see figure 4).
With respect to claims 11-16, Steinberg discloses the limitations of claim 8 as previously stated. The PIC as taught forms the PIC part of the device of the claims. The limitations further defining the device in claims 11-16 are an intended use of the PIC as claimed in claim 8 and do not further define the PIC.
20. A method for manufacturing a photonic integrated circuit (PIC), comprising: forming an electro-absorption modulator (EAM) (compact differential traveling wave electro-absorption modulator CD-TWEAM 100 is interpreted as the EAM) by forming, on the PIC:
an active region (103) of the EAM; and
at least one waveguide (102) of the EAM;
forming at least one metallization layer (the layer including the first and second biasing networks) on the PIC; and
forming, within the at least one metallization layer: a first biasing network providing both biasing and termination to the EAM (termination load 208A and biasing element 210A and all electrically connected components are together interpreted as the first biasing network), the first biasing network being electrically coupled to a first electrode of the EAM and comprising: a first inductor (see column 11, line 64 – column 12, line 10, the biasing element 210A is an inductor); and a first resistor (the termination load comprises a resistor providing resistance, see column 11, line 64 – column 12, line 10) electrically coupled in series with the first inductor (see figure 4); and a second biasing network (the corresponding “B” labeled elements are interpreted as the second biasing network), the second biasing network being electrically coupled to a second electrode of the EAM and comprising: a second inductor; and a second resistor electrically coupled in series with the second inductor (see figure 4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M BEDTELYON whose telephone number is (571)270-1290. The examiner can normally be reached 8:00am - 4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/John Bedtelyon/Primary Examiner, Art Unit 2874
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