DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 29 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 30 of U.S. Patent No. 11,967,897. Although the claims at issue are not identical, they are not patentably distinct from each other because Claim 29 of the instant application recites a method operating/controlling a switching network in a first and second path. The first path including serially connected first and second pump capacitors and the second path including serially connected first balancing capacitor and a third pump capacitor. This is essentially the same operation as how the capacitor network of the power converter of claim 30 of U.S. Patent No. 11,967,897 is controlled. Wherein Patent No. 11,967,897 has a first and path. Wherein the first path including a first and second fly capacitor (i.e., equivalent to pump capacitors) connected in series and a second path having serially connected rebalancing (i.e., equivalent to balancing capacitors) and third fly capacitor. It would have been obvious to use the power converter of claim 30 of Patent No. 11,967,897 to perform the method of claim 29 of the instant invention for the purpose of having a device capable of providing the claimed method.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 22, 23, 38 and 40 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lesso (USPN 7,990,742).
With respect to claim 22, Lesso discloses, in Figs. 11a-12b, a circuit (1410 and 1420 operated in the phases shown in Figs. 11a-12b), comprising:
an input terminal (+VDD terminal);
an output terminal (VOUT+ terminal); and
a switched-capacitor circuit (1410), comprising:
a plurality of pump capacitors (Cf1 and Cf2), a plurality of balancing capacitors (CR1 and CR2 which balance/maintain the output voltage at a desired level), and a switching network (S1-S8), comprising:
a plurality of first switches (e.g., S2 and S8), wherein each of the first switches is coupled to one of the pump capacitors and to one of the balancing capacitors (S2 connected to Cf1 and CR1, S8 connected to CR2 and Cf2), and
a plurality of second switches (e.g., S1 and S4), wherein each of the second switches is coupled to one of the balancing capacitors and to either the input terminal (S1 connects CR1 to VDD+, see Figs. 11a and 11b) or to a ground terminal (S4 is connected to both CR2 and CR1 and ground).
With respect to claim 23, the circuit of claim 22, wherein the switching network further comprises a plurality of third switches (e.g. S3 and S5), wherein each of the third switches is coupled to two of the pump capacitors (s3 connected to the top plates of Cf1 and Cf2, S5 connected to the bottom plates of Cf1 and Cf2).
With respect to claim 38, Lesso discloses, in Figs. 4-8, an apparatus (charge pump of Figs. 4a and 4b, operational details disclosed in Figs. 5a-8) comprising:
a plurality of capacitors (Cf1, Cf2, CR1 and CR2),
a switching network (S1-S8 of Fig. 4b, see also Figs. 5a, 6a and 7a), and
a controller (420) configured to cause the switching network to configure the plurality of capacitors to alternately (the control is cyclical and alternately, see control of switches as shown in Fig. 8) form first (at least one of the networks shown in Figs. 5a/b, 6a/b and 7a/b) and second (a different one of the at least one of the networks shown in Figs. 5a/b, 6a/b and 7a/b) capacitor networks, wherein the first capacitor network comprises a first path having a first plate of a first capacitor (all of the capacitors networks includes a first path having a first plate of Cf1, i.e., the positive plate of Cf1. For example, the “first path” is interpreted as the path shown in Figs. 5a and 5b which includes the positive terminal of Cf1. Alternately the first network may be interpreted as the network of Fig. 6a/b. Wherein Figs 6a and 6b includes a first path from Vout+ to ground using the Cf1 capacitor. Cf1 having the positive terminal, i.e., the “first” terminal), wherein the second capacitor network comprises a second path (e.g., second network and path is interpreted as the network shown in Figs. 7a and 7b) having the first plate of the first capacitor (positive termina of Cf1) coupled to a first plate of a second capacitor (positive terminal of Cf2 coupled to the first plate of Cf21, see Fig. 7b), wherein, the controller is configured such that, when the first plate of the first capacitor is to be coupled to the first plate of the second capacitor to change from the switching network forming the first capacitor network to the switching network forming the second capacitor network, a first voltage at the first plate of the first capacitor is substantially the same as a second voltage at the first plate of the second capacitor (the voltage one the first plates of each capacitor are always the same voltage of VDD/2 in Figs. 5a/b, 6a/b and 7a/b. Thus, the circuit operates as claimed).
With respect to claim 40, the apparatus of claim 38, wherein the controller is configured to alternatingly form the first and second capacitor networks to convert a first voltage at a first terminal a second voltage at a second terminal (converter VDD to VDD/2).
Claim(s) 29, 31-32 and 35 and 37 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kamijo (USPN 7,538,763).
With respect to claim 29, Kamijo discloses, in Figs. 1-5B, 18 and 20, a method (method of operating Fig. 3, construction and operational details disclosed in Figs. 1-2 and 4-5B and/or the method of operating the circuit of Figs. 18 and 20. Note, Figs. 18 and 20 operate in essentially the same fashion as the circuit of Fig. 1-5B except Figs. 18 and 20 include an additional second parallel connected charge pump, i.e., 470, that is operated in essentially the same way as the first charge pump of Fig. 2 with inverted control signals by 480 of Fig. 18. Thus, the rejections will be discussed with respect to Figs. 1-5B, unless otherwise noted, to aid in explanation.), comprising:
controlling a switching network of a switched-capacitor circuit (controlling the switched-capacitor of Fig. 3 in the second and first periods as shown in Figs. 2 and 4-5B. As well as the second switching network of the second switched capacitor network of 470 of Fig. 18 and Fig. 20) to cause a plurality of pump capacitors of the switched-capacitor circuit (Cu1-Cu4, the pumped capacitors are responsible for pumping the voltage V up to a high voltage level 5*V, see Figs. 1, 2, 18 and 20) and a plurality of balancing capacitors of the switched-capacitor circuit (CS1-CS4, balancing capacitors responsible for balancing/stabilizing the output voltages) to form a first path (path of the 2*V/Third power supply line to 5*V/sixth power supply line via Cu4 to Cu2 of the second period of Figs. 2 and 5B), wherein the first path comprises a first pump capacitor of the plurality of pump capacitors (one of Cu4 to Cu2 in the second period as shown in Figs. 2 and 5B) and a second pump capacitor of the plurality of pump capacitors (other one of Cu4 to Cu2 in the second period as shown in Figs. 2 and 5B) in series (Cu4 to Cu2 are serially connected); and
controlling the switching network to cause the pump capacitors and the balancing capacitors to form a second path (path associated with first period of Fig. 2 and 5A), wherein the second path comprises a first balancing capacitor (e.g., Cs1) and a third pump capacitor (e.g., Cu1) in series (Cs1 and Cu1 are serially connected between 2*V/VL-3 and VSS/VL-1).
With respect to claim 31, the method of claim 29, wherein the switched-capacitor circuit comprises a two-phase Dickson charge pump (Fig. 3 is a two-phase, first and second period/phase, Dickson charge pump).
With respect to claim 32, the method of claim 29, further comprising:
controlling the switching network to cause the pump capacitors and the balancing capacitors to form a third path (first period of Cu4-B to Cu1-B), wherein the third path comprises a fourth pump capacitor (one of Cu4-B to Cu1-B) of the plurality of pump capacitors and the third pump capacitor in series (in the first period of the second charge pump Cu1-B and Cu1-A are serially connected between 2*V and VSS, see Fig. 20); and
controlling the switching network to cause the pump capacitors and the balancing capacitors to form a fourth path (path of CS1 to third supply line, third supply to fourth supply line via Cs2 and path from fourth supply to fifth supply line via Cs3 and path from fifth power supply to the sixth power supply via Cu4 in the second period of Figs. 2 and 20), wherein the fourth path comprises the first balancing capacitor (CS1) and the second pump capacitor (e.g., Cu4) in series (the capacitors are serially connected in the above path).
With respect to claim 35, the method of claim 32, wherein each of the pump capacitors has substantially the same capacitance as each of the balancing capacitors (the pump capacitors and balancing capacitors have the same capacitance value of “c”, see Col. 13 line 48-52).
With respect to claim 37, the method of claim 32, wherein the plurality of pump capacitors comprises a first pump capacitor (Cu1-A of Fig. 20), a second pump capacitor (Cu1-B of Fig. 20), a third pump capacitor (Cu4-A of Fig. 20), and a fourth pump capacitor (Cu4-B of Fig. 20), the method further comprising:
selectably connecting the first and second pump capacitors to either a ground terminal (in the first period the bottom terminal of Cu1-A is connected to VSS; in the second period the bottom terminal of Cu1-B is connected to VSS) or to a first balancing capacitor of the plurality of balancing capacitors (in the second period the top terminal of Cu1-A is connected to Cs2; in the first period the top terminal of Cu1-B is connected to Cs2. Further note that the above recitation is in the alternative and not required by the claim); and
selectably connecting the third and fourth pump capacitors to either an output terminal (during the second period the top terminal of Cu4-A is connected to the 5*V output; during the first period the top terminal of Cu4-B is connected to the 5*V output) or to a second balancing capacitor of the plurality of balancing capacitors (during the first period Cu-4A is connected in parallel to Cs3; during the second period Cu4B is connected in parallel to Cs3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 39 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Lesso (USPN 7,990,742).
With respect to claim 39, the apparatus of claim 38, wherein:
the first path and the second path have different numbers of capacitors;
the first path and the second path have substantially the same capacitance;
the first capacitor network comprises a third path, wherein the first path and the third path have substantially the same capacitance; and/or
the first capacitor network further comprises a third path, wherein the first path, the second path, and the third path have substantially the same capacitance (the above clause includes an and/or statement. Thus, the claims may read on only the “or” state associated with the last clause when the “first capacitor network is interpreted as Figs. 6a and 6b, the first network includes a third path CR1 from Vout+ to ground. The second path is shown in 7a and 7b. As can be seen 6a/b and 7a/b both include paths having two parallel connected capacitors, e.g., Cf1 and CR1 of Figs. 6a/b and Cf1 with Cf2 of Figs. 7a/b. Furthermore, Lesso anticipates that Cf1, Cf2, CR1 and CR2 may be the same size depending on load conditions and ripple tolerance, see Col. 8 lines 17-24. The capacitances may be the same or different as desired. When the capacitances are the same size the circuit will operate as claimed).
Assuming, arguendo, that Lesso merely suggests that the Cf1, Cf2, CR1 and CR2 may be the same value and does not explicitly disclose such a construction. It would have been obvious to size the capacitance of Cf1, Cf2, CR1 and CR2 such that the areas are equal depending on the load conditions and ripple requirement, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so set the capacitances to a desired level according to loading, frequency and ripple requirements as suggested by Lesso.
Claim(s) 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kamijo (USPN 7,538,763) in view of Arigong et al. (USPN 10,236,833).
With respect to claim 36, the method of claim 35, wherein the pump capacitors each have a first area, wherein the balancing capacitors each have a corresponding second area (the capacitors inherently haven an associated “area”).
However, Kamijo fails to disclose the specific details of the areas of the pump capacitors and the balancing capacitors and thus fails to disclose “wherein the first and second areas are different”.
Nevertheless, it is old and well-known that the capacitance of a capacitor is controlled by multiple variables such as area of the upper and lower plates, thickness of the dielectric region, and the dielectric constant of the dielectric material. This is further evidenced in Col. 8 lines 44-49 of Arigong et al. Therefore, it can be seen that one of ordinary skill in the art is capable of constructing a first capacitor and second capacitor having different areas (e.g., areas of the upper and lower plates) and still maintain the same overall capacitance by adjusting another variable, such as the dielectric constant of the dielectric material of the capacitor, between the first and second capacitors in proportion to the difference of the area of the capacitors as evidenced by Arigong et al. It would have been obvious to construct the pumping and balancing capacitors of Kamijo such that they have different areas and different, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so to optimize circuit layout and construction of the capacitors.
Claim(s) 41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lesso (USPN 7,990,742) in view of Arigong et al. (USPN 10,236,833).
With respect to claim 41, Lesso discloses the apparatus of claim 38, wherein the first capacitor is a pump capacitor (Cf1 is a pumping capacitor for setting the desired output voltage level), wherein the first path further comprises a balancing capacitor (e.g., CR1, when the first path is interpreted as the first path/network. CR1 is a balancing capacitor in that it maintains the balance of the output voltage level even under different loading conditions), wherein the capacitance of the first capacitor and the balancing capacitor are substantially the same (Lesso anticipates that Cf1, Cf2, CR1 and CR2 may be the same size depending on load conditions and ripple tolerance, see Col. 8 lines 17-24. The capacitances may be the same or different as desired).
Lesso fails to disclose the specific areas of the capacitors. Thus, Lesso fails to disclose “wherein the first capacitor has a first area, wherein the balancing capacitor has a corresponding second area, and wherein the first and second areas are different”.
Nevertheless, it is old and well-known that the capacitance of a capacitor is controlled by multiple variables such as area of the upper and lower plates, thickness of the dielectric region, and the dielectric constant of the dielectric material. This is further evidenced in Col. 8 lines 44-49 of Arigong et al. Therefore, it can be seen that one of ordinary skill in the art is capable of constructing a first capacitor and second capacitor having different areas (e.g., areas of the upper and lower plates) and still maintain the same overall capacitance by adjusting another variable, such as the dielectric constant of the dielectric material of the capacitor, between the first and second capacitors in proportion to the difference of the area of the capacitors as evidenced by Arigong et al. It would have been obvious to construct the pumping and balancing capacitors of Lesso such that they have different areas, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so to optimize circuit layout and construction of the capacitors.
Allowable Subject Matter
Claims 24-28, 30 and 33-34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/ Primary Examiner, Art Unit 2849