DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 29 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 30 of U.S. Patent No. 11,967,897. Although the claims at issue are not identical, they are not patentably distinct from each other because Claim 29 of the instant application recites a method operating/controlling a switching network in a first and second path. The first path including serially connected first and second pump capacitors and the second path including serially connected first balancing capacitor and a third pump capacitor. This is essentially the same operation as how the capacitor network of the power converter of claim 30 of U.S. Patent No. 11,967,897 is controlled. Wherein Patent No. 11,967,897 has a first and path. Wherein the first path including a first and second fly capacitor (i.e., equivalent to pump capacitors) connected in series and a second path having serially connected rebalancing (i.e., equivalent to balancing capacitors) and third fly capacitor. It would have been obvious to use the power converter of claim 30 of Patent No. 11,967,897 to perform the method of claim 29 of the instant invention for the purpose of having a device capable of providing the claimed method.
Specification
Claim 37 is objected to because of the following informalities:
The recitation of “a fourth pump capacitor” on line 3 should be changed to -- the fourth pump capacitor --, since antecedent basis for the fourth pump capacitor is providing in claim 32 . Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 29, 31-32 and 35 and 37 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kamijo (USPN 7,538,763).
With respect to claim 29, Kamijo discloses, in Figs. 1-5B, 18 and 20, a method (method of operating Fig. 3, construction and operational details disclosed in Figs. 1-2 and 4-5B and/or the method of operating the circuit of Figs. 18 and 20. Note, Figs. 18 and 20 operate in essentially the same fashion as the circuit of Fig. 1-5B except Figs. 18 and 20 include an additional second parallel connected charge pump, i.e., 470, that is operated in essentially the same way as the first charge pump of Fig. 2 with inverted control signals by 480 of Fig. 18. Thus, the rejections will be discussed with respect to Figs. 1-5B, unless otherwise noted, to aid in explanation.), comprising:
controlling a switching network of a switched-capacitor circuit (controlling the switched-capacitor of Fig. 3 in the second and first periods as shown in Figs. 2 and 4-5B. As well as the second switching network of the second switched capacitor network of 470 of Fig. 18 and Fig. 20) to cause a plurality of pump capacitors of the switched-capacitor circuit (Cu1-Cu4, the pumped capacitors are responsible for pumping the voltage V up to a high voltage level 5*V, see Figs. 1, 2, 18 and 20, see Cu1a-Cu4a of Fig. 2) and a plurality of balancing capacitors of the switched-capacitor circuit (CS1-CS4, balancing capacitors responsible for balancing/stabilizing the output voltages) to form a first path (path of the 2*V/Third power supply line to 5*V/sixth power supply line via Cu4 to Cu2 of the second period of Figs. 2 and 5B, see also Cu4a to Cu2a of Fig. 20), wherein the first path comprises a first pump capacitor of the plurality of pump capacitors (one of Cu4/Cu4a to Cu2/Cu2a in the second period as shown in Figs. 2, 5B and 20) and a second pump capacitor of the plurality of pump capacitors (other one of Cu4/Cu4a to Cu2/Cu2a in the second period as shown in Figs. 2, 5B and 20) in connected series (Cu4/Cu4a to Cu2/Cu2a are serially connected); and
controlling the switching network to cause the plurality of pump capacitors and the plurality of balancing capacitors to form a second path (path associated with first period of Figs. 2, 5A and 20), wherein the second path comprises a first balancing capacitor (e.g., Cs1) and a third pump capacitor (e.g., Cu1/Cua1) connected in series (Cs1 and Cu1/Cu1a are serially connected between 2*V/VL-3 and VSS/VL-1).
With respect to claim 31, the method of claim 29, wherein the switched-capacitor circuit comprises a two-phase Dickson charge pump (Fig. 3 is a two-phase, first and second period/phase, Dickson charge pump), wherein the first pump capacitor is selectively connected in series with the second pump capacitor (the first and second pump capacitors within Cu2-Cu4/Cu2a-Cu4a are selectively connected, via switches SW4-SW10 of Fig. 3, such that the above capacitors are always serially connected, e.g., in both the first period of Fig. 2 and the second period of Fig. 2. Thus, the first pump capacitor and the second pump capacitor are “selectively” connected in series via the switches), and wherein the first balancing capacitor is selective connected in series with the third pump capacitor (in the second period of Fig. 2 Cu1/Cu1a and Cs1 are connected in parallel and in the first period Fig. 2 Cu1/Cu1a and Cs1 are connected in series via the switches. Thus the first balancing capacitor and third pump capacitor are “selectively” connected in series during the first period)
With respect to claim 32, the method of claim 29, further comprising:
controlling the switching network to cause the pump capacitors and the balancing capacitors to form a third path (first period of Cu4-B to Cu1-B), wherein the third path comprises a fourth pump capacitor (one of Cu4-B to Cu1-B) of the plurality of pump capacitors and the third pump capacitor in connected series (in the first period of the second charge pump Cu1-B and Cu1-A are serially connected between 2*V and VSS, see Fig. 20); and
controlling the switching network to cause the pump capacitors and the balancing capacitors to form a fourth path (path of CS1 to third supply line, third supply to fourth supply line via Cs2 and path from fourth supply to fifth supply line via Cs3 and path from fifth power supply to the sixth power supply via Cu4 in the second period of Figs. 2 and 20), wherein the fourth path comprises the first balancing capacitor (CS1) and the second pump capacitor (e.g., Cu4) in connected series (the capacitors are serially connected in the above path).
With respect to claim 35, the method of claim 32, wherein each of the pump capacitors has substantially the same capacitance as each of the balancing capacitors (the pump capacitors and balancing capacitors have the same capacitance value of “c”, see Col. 13 line 48-52).
With respect to claim 37, the method of claim 32, wherein the plurality of pump capacitors comprises a fourth pump capacitor (Cu4-B of Fig. 20), the method further comprising:
selectably connecting the first and second pump capacitors to either a ground terminal or to a first balancing capacitor of the plurality of balancing capacitors (when the first pump capacitor is selected as Cu2/Cu2A and the second pump capacitor is selected as Cu3/Cu3A in the second period Cu2/Cu2A is selectively connected in parallel with Cs1 and the bottom terminal of Cu3/Cu3A is connected to the top terminal of Cs1 at the 2*V terminal. Note the above limitation is stated in the alternative and thus only one of the above alternatives is required to meet the claimed limitations); and
selectably connecting the third and fourth pump capacitors to either an output terminal or to a second balancing capacitor of the plurality of balancing capacitors (Cu4/Cu4B is connected to the top terminal of CS3 at the VL-5 line during the first period. Additionally, Cu1/Cu1A is connected to CS3 via CS1-CS2 during the first period. Thus, the circuit is connected as claimed. Note the above limitation is stated in the alternative and thus only one of the above alternatives is required to meet the claimed limitations).
Claim(s) 38 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lesso (USPN 7,990,742).
With respect to claim 38, Lesso discloses, in Figs. 4-8, an apparatus (charge pump of Figs. 4a and 4b, operational details disclosed in Figs. 5a-8) comprising:
a plurality of capacitors (Cf1, Cf2, CR1 and CR2),
a switching network (S1-S8 of Fig. 4b, see also Figs. 5a, 6a and 7a), and
a controller (420) configured to cause the switching network to configure the plurality of capacitors to alternately (the control is cyclical and alternately, see control of switches as shown in Fig. 8) form first (at least one of the networks shown in Figs. 5a/b, 6a/b and 7a/b) and second (a different one of the at least one of the networks shown in Figs. 5a/b, 6a/b and 7a/b) capacitor networks, wherein the first capacitor network comprises a first path having a first capacitor (Cf1. For example, the “first path” is interpreted as the path shown in Figs. 5a and 5b. Alternately the first network may be interpreted as the network of Fig. 6a/b. Wherein Figs 6a and 6b includes a first path from Vout+ to ground using the Cf1 capacitor. Cf1 is the first capacitor), wherein the second capacitor network comprises a second path (e.g., second network and path is interpreted as the network shown in Figs. 7a and 7b) having the first capacitor (Cf1) and a second capacitor (Cf2) having an anode connected to an anode of the first capacitor (“anode” is interpreted as the positive voltage terminal of each capacitor. As can be seen in Fig. 7B the positive voltage terminal of Cf1 and Cf2 are connected together), wherein, the controller is configured such that, at a time when the anode of the first capacitor is to be connected to the anode of the second capacitor to change from the switching network forming the first capacitor network to the switching network forming the second capacitor network, a first voltage at the anode of the first capacitor is substantially the same as a second voltage at the anode of the second capacitor (the voltage one the positive voltage terminal/anode of each capacitor are always the same voltage of VDD/2 in Figs. 5a/b, 6a/b and 7a/b. Thus, the circuit operates as claimed and provides the functional limitations as claimed).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 39 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Lesso (USPN 7,990,742).
With respect to claim 39, the apparatus of claim 38, wherein:
the first path and the second path have different numbers of capacitors;
the first path and the second path have substantially the same capacitance;
the first capacitor network comprises a third path, wherein the first path and the third path have substantially the same capacitance; and/or
the first capacitor network further comprises a third path, wherein the first path, the second path, and the third path have substantially the same capacitance (the above clause includes an and/or statement. Thus, the claims may read on only the “or” state associated with the last clause when the “first capacitor network is interpreted as Figs. 6a and 6b, the first network includes a third path CR1 from Vout+ to ground. The second path is shown in 7a and 7b. As can be seen 6a/b and 7a/b both include paths having two parallel connected capacitors, e.g., Cf1 and CR1 of Figs. 6a/b and Cf1 with Cf2 of Figs. 7a/b. Furthermore, Lesso anticipates that Cf1, Cf2, CR1 and CR2 may be the same size depending on load conditions and ripple tolerance, see Col. 8 lines 17-24. The capacitances may be the same or different as desired. When the capacitances are the same size the circuit will operate as claimed).
Assuming, arguendo, that Lesso merely suggests that the Cf1, Cf2, CR1 and CR2 may be the same value and does not explicitly disclose such a construction. It would have been obvious to size the capacitance of Cf1, Cf2, CR1 and CR2 such that the areas are equal depending on the load conditions and ripple requirement, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so set the capacitances to a desired level according to loading, frequency and ripple requirements as suggested by Lesso.
Claim(s) 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kamijo (USPN 7,538,763) in view of Arigong et al. (USPN 10,236,833).
With respect to claim 36, the method of claim 35, wherein the pump capacitors each have a first area, wherein the balancing capacitors each have a corresponding second area (the capacitors inherently haven an associated “area”).
However, Kamijo fails to disclose the specific details of the areas of the pump capacitors and the balancing capacitors and thus fails to disclose “wherein the first and second areas are different”.
Nevertheless, it is old and well-known that the capacitance of a capacitor is controlled by multiple variables such as area of the upper and lower plates, thickness of the dielectric region, and the dielectric constant of the dielectric material. This is further evidenced in Col. 8 lines 44-49 of Arigong et al. Therefore, it can be seen that one of ordinary skill in the art is capable of constructing a first capacitor and second capacitor having different areas (e.g., areas of the upper and lower plates) and still maintain the same overall capacitance by adjusting another variable, such as the dielectric constant of the dielectric material of the capacitor, between the first and second capacitors in proportion to the difference of the area of the capacitors as evidenced by Arigong et al. It would have been obvious to construct the pumping and balancing capacitors of Kamijo such that they have different areas and different, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so to optimize circuit layout and construction of the capacitors.
Claim(s) 41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lesso (USPN 7,990,742) in view of Arigong et al. (USPN 10,236,833).
With respect to claim 41, Lesso discloses the apparatus of claim 38, wherein the first capacitor is a pump capacitor (Cf1 is a pumping capacitor for setting the desired output voltage level), wherein the first path further comprises a balancing capacitor (e.g., CR1, when the first path is interpreted as the first path/network. CR1 is a balancing capacitor in that it maintains the balance of the output voltage level even under different loading conditions), wherein the capacitance of the first capacitor and the balancing capacitor are substantially the same (Lesso anticipates that Cf1, Cf2, CR1 and CR2 may be the same size depending on load conditions and ripple tolerance, see Col. 8 lines 17-24. The capacitances may be the same or different as desired).
Lesso fails to disclose the specific areas of the capacitors. Thus, Lesso fails to disclose “wherein the first capacitor has a first area, wherein the balancing capacitor has a corresponding second area, and wherein the first and second areas are different”.
Nevertheless, it is old and well-known that the capacitance of a capacitor is controlled by multiple variables such as area of the upper and lower plates, thickness of the dielectric region, and the dielectric constant of the dielectric material. This is further evidenced in Col. 8 lines 44-49 of Arigong et al. Therefore, it can be seen that one of ordinary skill in the art is capable of constructing a first capacitor and second capacitor having different areas (e.g., areas of the upper and lower plates) and still maintain the same overall capacitance by adjusting another variable, such as the dielectric constant of the dielectric material of the capacitor, between the first and second capacitors in proportion to the difference of the area of the capacitors as evidenced by Arigong et al. It would have been obvious to construct the pumping and balancing capacitors of Lesso such that they have different areas, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so to optimize circuit layout and construction of the capacitors.
Allowable Subject Matter
Claims 22-28, 30, 33-34 and 40 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 4/14/2026 have been fully considered but they are not persuasive.
With respect to claim 29, Applicant argues that “Cu1 through Cu4 are not connected in series”. The above argument is not persuasive, since it can be seen that the above Cu1-Cu4 are always serially connected. Clearly, the above capacitors are not connected in parallel, anti-parallel, nor anti-series. Thus, the above capacitors must be serially connected. Upon visual inspection it can be seen that in the first period Cu4-Cu2 (and Cu4-Cu1) are serially connected between VL-5/4*V to V/VL-2 (e.g., VSS/VL-1 when including Cu1). It is known when the negative (lower voltage) terminal of a first capacitor connected having a positive (higher voltage) terminal connected to a larger voltage is connected to the positive (higher voltage) terminal of a second capacitor having a negative (lower voltage) terminal that is connected to a voltage that is lower than at the positive terminal of the first capacitor, the above first and second capacitors are serially connected. This is further evidenced in Figs. 5a and 5b of Lesso (USPN 7,990,742), see Col. 7 lines 56-60. As can be seen Cu4-Cu2 (and Cu4-Cu1) are serially connected in the same fashion. Applicant further states, that “in the second period”…”Cu4 is connected to Cu3, Cs4 and Cs3”…and “Cu4 is not connected in series with any Cu3, Cs4 and Cs3”. The above argument is not persuasive for the reasons discussed above. The fact that Cu4 is connected to Cu3, Cs4 and Cs3 does not mean that Cu4 is not connected Cu3, Cs4 and Cs3. It is noted that Cu3 and Cu4 are always serially connected and the Cu4 is serially connected to Cs4 in the first period serially connected to Cs3 in the second period of Fig. 2.
The argument that “Cu1 through Cu4 are not connected in series with Cs1 through Cs4” sense claim 29 does not require the pump capacitors (Cu1 through Cu4 of the rejection) to be in series with the balance capacitors (Cs1-Cs4 of the rejection). Rather the claims merely require the first and second pump capacitor connected in series in a first path (the pump capacitors are always connected in series) and only “a third capacitor” and “a first balancing” capacitor being serially connected in the second path (during the first period Cs1 and Cu1 are serially connected between VL-3/2*V and VSS). Thus, the circuit is connected and operative as claimed. Furthermore, in response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., that “Cu1 through Cu4 are not connected in series with Cs1 through Cs4”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The argument that Lesso fails “to disclose the anodes of capacitors being connected” is not persuasive. The “anode of a capacitor” is interpreted as the positively charged electrode/plate of a capacitor (i.e., the terminal that is connected to the positive voltage of the capacitor) which is consistent with the term “anode”. As can be seen in each figure 5a-7b each capacitor has an indicated positively charged terminal (i.e., anode) with a “+” symbol. Thus each capacitor has an anode as indicated by Lesso. Furthermore, in Fig. 7b the anode (i.e., positively charged terminal/positive voltage terminal) of both Cf1 and Cf2 are connected together at N15/N18. Thus, Less discloses the anodes of Cf1 and Cf2 being connected. Moreover, the anodes of Cf1 and Cf2 (i.e., the voltages across Cf1 and Cf2) are always at the VDD/2 level in Figs. 5a-7b. Thus, the voltage level at the anodes will always be equal at all times. Therefore, Lesso provides for the functional limitations of claim 38.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
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