DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS), submitted on 4/24/2024, 5/6/2026, 6/30/2026, are being considered by the examiner.
Objections
Claims 1 and 10 are objected. A claim limitation “a switchable PIM array” should be read “a switchable processing-in-memory (PIM) array”. Appropriate corrections are required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) ELEMENT IN CLAIM FOR A COMBINATION.—An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as "configured to" or "so that"; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitations use a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are a reconfigurable memory unit, a Computation unit, and a computation control module in claims 1 and 11.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejection – 35 U.S.C. § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of pre-AIA 35 U.S.C. 112, second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter, which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 recites "the operation mode of each of the memory cells ". There is insufficient antecedent basis for this limitation in the claim. Therefore, claim 1 and its dependent claims are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph. An amendment with "the operation mode of each of the triple-mode memory cells" will address the issue.
Claims 9-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter, which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. The independent claim 9 recites "reconfigure the dataflow ". It is noted that claim 9 previously recites “dataflows”. However, it is not clear from the claim language which one of these dataflows that “the dataflow” refers to. As s result, claim 9 and its dependent claims are indefinite and are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chi (PRIME: A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory), (“Chi”).
Regarding claim 1, Chi meets the claim limitations as follow.
A dynamic random access memory (DRAM) memory (ReRAM has been considered as a cost-efficient replacement of DRAM to build next-generation main memory) [Chi: page 28] comprising: a switchable PIM array (In this work, we propose a novel PIM architecture for efficient NN computation built upon ReRAM crossbar arrays, called PRIME) [Chi: page 28] including a plurality of triple-mode memory cells each operating in any one operation mode among a computation mode, a memory mode, and a data conversion mode (PRIME directly leverages ReRAM cells to perform computation without the need for extra PUs. To achieve this, as shown in Figure 3(c), PRIME partitions a ReRAM bank into three regions: memory (Mem) subarrays, full function (FF) subarrays, and Buffer subarrays) [Chi: page 30; Fig. 3]; a reconfigurable memory unit configured to operate as a computation control module for supporting a computation function or a buffer for data buffering (PRIME is a morphable ReRAM based main memory architecture, where a portion of ReRAM crossbar arrays are enabled with the NN computation function, referred as full function subarrays. When NN applications are running, PRIME can execute them with the full function subarrays to improve performance or energy efficiency; while no NN applications are executed, the full function subarrays can be freed to provide extra memory capacity) [Chi: page 29; Fig. 4] depending on the operation mode of each of the memory cells (reconfigurable SA with counters for multi-level outputs, and added ReLU and 4-1 max pooling function units; (D) connection between the FF and Buffer subarrays) [Chi: Fig. 4]; and a memory controller (PRIME controller) [Chi: Fig. 4] configured to determine the operation mode of each of the memory cells by external control, wherein the DRAM memory is convertible to any one of a Computation unit, a memory (The morphing between memory and computation modes involves several steps. Before the FF subarrays switch from memory mode to computation mode, PRIME migrates the data stored in the FF subarrays to certain allocated space in Mem subarrays, and then writes the synaptic weights to be used by computation into the FF subarrays. When data preparations are ready, the peripheral circuits are reconfigured by the PRIME controller, and the FF subarrays are switched to computation mode and can start to execute the mapped NNs. After completing the computation tasks, the FF subarrays are switched back to memory mode through a wrap-up step that reconfigures the peripheral circuits) [Chi: page 32; Fig 5], and a data converter (In a typical ReRAM-based neuromorphic computing system [10], DACs and ADCs are used for input and output signal conversions; in a ReRAM-based memory system, SAs and write drivers are required for read and write operations. Yet, SAs and
ADCs serve similar functions, while write drivers and DACs do similar functions. In PRIME, instead of using both, we reuse SAs and write drivers to serve ADC and DAC functions by slightly modifying the circuit design. Second, we enable the FF subarrays to flexibly and efficiently morph between memory and computation modes) [Chi: page 32; Fig. 5].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims under pre-AIA 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of pre-AIA 35 U.S.C. 103(c) and potential pre-AIA 35 U.S.C. 102(e), (f) or (g) prior art under pre-AIA 35 U.S.C. 103(a).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chi (PRIME: A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory), (“Chi”), in view of Kim et al. (US Patent Application Publication US 2024/0028297 A1), (“Kim”).
Regarding claim 1, Mittal meets the claim limitations as follow.
wherein the switchable PIM array (In this work, we propose a novel PIM architecture for efficient NN computation built upon ReRAM crossbar arrays, called PRIME) [Chi: page 28]; (PRIME is a morphable ReRAM based main memory architecture, where a portion of ReRAM crossbar arrays are enabled with the NN computation function, referred as full function subarrays) [Chi: page 29; Fig. 4]) comprises: a memory cell array (ReRAM crossbar arrays, called PRIME) [Chi: page 28] including a plurality of computation rows each formed in a unit of computation (We choose to configure the adjacent memory subarray to the FF subarrays as the Buffer subarray, which is close to both the FF subarrays and the global row buffer so as to minimize the delay. We do not utilize the local row buffer because it is not large enough to serve typical NNs) [Chi: page 32; Fig. 4] including a 1-bit memory cell (so-called "sign cell") indicating sign and a predetermined-bit memory cell (so-called "magnitude cell") indicating magnitude to process signals of certain bits by separation into sign and magnitude; a global input driver configured to transmit input data or a control signal for determining the operation modes of the memory cells to the memory cell array (The morphing between memory and computation modes involves several steps. Before the FF subarrays switch from memory mode to computation mode, PRIME migrates the data stored in the FF subarrays to certain allocated space in Mem subarrays, and then writes the synaptic weights to be used by computation into the FF subarrays. When data preparations are ready, the peripheral circuits are reconfigured by the PRIME controller, and the FF subarrays are switched to computation mode and can start to execute the mapped NNs. After completing the computation tasks, the FF subarrays are switched back to memory mode through a wrap-up step that reconfigures the peripheral circuits) [Chi: page 32; Fig 5]; and peripheral logic including ADC logic and an inter-bit parallel addition tree to control an operation of the memory cell array, and responsible for interfacing with external devices (In a typical ReRAM-based neuromorphic computing system [10], DACs and ADCs are used for input and output signal conversions; in a ReRAM-based memory system, SAs and write drivers are required for read and write operations. Yet, SAs and ADCs serve similar functions, while write drivers and DACs do similar functions. In PRIME, instead of using both, we reuse SAs and write drivers to serve ADC and DAC functions by slightly modifying the circuit design. Second, we enable the FF subarrays to flexibly and efficiently morph between memory and computation modes) [Chi: page 32; Fig. 5].
Mittal does not explicitly disclose the following claim limitations (Emphasis added).
a 1-bit memory cell (so-called "sign cell") indicating sign and a predetermined-bit memory cell (so-called "magnitude cell") indicating magnitude to process signals of certain bits by separation into sign and magnitude.
However, in the same field of endeavor Kim further discloses the deficient claim limitations as follows:
a 1-bit memory cell (so-called "sign cell") indicating sign and a predetermined-bit memory cell (so-called "magnitude cell") indicating magnitude to process signals of certain bits by separation into sign and magnitude ((the 2nd weight bit W02 is a sign bit, and the 1st weight bit W01 and the 0th weight bit W00 are magnitude bits) [Kim: para. 0062; Figs. 1-4]; (a sign bit and a magnitude bit, the sign bit corresponding to the sign information, and the magnitude bit is output from another memory cell that is different from a memory cell from which the sign bit is read, among the one or more memory cells, wherein when there are a plurality of magnitude bits, the plurality of magnitude bits are read sequentially from the least significant bit to the most significant bit from the one or more memory cells after the sign bit has been read) [Kim: claim 4; Figs. 1-4].
It would have been obvious to one with an ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Chi with Kim to program the system to implement of Kim’s method.
Therefore, the combination of Chi with Kim will enable the system to improve performance sich as MAC operations [Kim: para. 0010].
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Mittal (A Survey of ReRAM-Based Architectures for Processing-In-Memory and Neural Networks), (“Mittal”), in view of Kim et al. (US Patent Application Publication #), (“Kim”).
Regarding claim 9, Mittal meets the claim limitations as follow.
An artificial intelligence (AI) accelerator configured to train an AI neural network (PIM- and NN-based accelerators) [Mittal: Abstract], the AI accelerator comprising: a plurality of fixed memories exclusively operating as memories (a ReRAM-based pipelined design for accelerating both training and testing of CNNs. They divide MCAs into two types: memory and morphable. The morphable MCAs can perform both computation and data-storage and memory MCAs can only store data) [Mittal: page 84]; a plurality of switchable memories each switchable to any one of a calculator, a memory ((a ReRAM-based pipelined design for accelerating both training and testing of CNNs. They divide MCAs into two types: memory and morphable. The morphable MCAs can perform both computation and data-storage and memory MCAs can only store data) [Mittal: page 84]; (Chi et al. [43] proposed a PIM architecture for ReRAM-based main memory for accelerating NN computations. They divided a ReRAM bank into three types of subarrays: memory (Mem), buffer and full function (FF)) [Mittal: page 97-98; Fig. 25]), and a data converter (FF subarrays benefit from high bandwidth of in-memory data movement and ability to work in parallel to CPU. They noted that an SA performs similar function as an ADC and same is also true for write drivers and DACs. Hence, with only small modifications, they reused write drivers and SAs to perform the function of DAC and ADC, respectively. This sharing of periphery between computation and memory lowers the area overhead) [Mittal: page 98; Fig. 25]; a plurality of transmission links ((FF subarrays) [Mittal: page 98, Fig. 25]; (DDR bus) [Mittal: Fig. 24]; (IO bus) [Mittal: Fig. 35]; (shared data bus) [Mittal: page 83; Figs. 7, 37]) configured to connect dataflows between the fixed memories and the switchable memories so that the dataflows are reconfigurable ((To switch the FF subarrays from memory to compute mode, data stored in them are moved to memory subarrays. Then, weights of the mapped NNs are written to the FF subarrays and the periphery is reconfigured. Opposite process happens on change from compute to memory mode) [Mittal: page 98, Fig. 25]; (local wordlines and device driver. Thus, by merely changing the read-circuit, their technique computes bitwise operations on multiple memory rows. The output can be written to the I/O bus or another memory row. Since their technique performs row-level operations only, the software need to allocate data in PIM-aware manner. Their technique can perform operations at intra-subarray, inter-subarray or inter-bank levels. Their technique achieves higher energy efficiency and performance compared to general-purpose processor and DRAM-based PIM technique) [Mittal: page 96; Fig. 29]; and a dynamic core generator configured to determine fixed memories and switchable memories (This core can be dynamically reconfigured for handling various applications. For example, as shown in Figure 11, for three different applications
(A, B and C), the cores/tiles that work as analog/digital-computing unit or memory unit can be altered. The parallelism of MCA is leveraged for performing compute and storage operations. Further, the resources are allocated in a manner to best match the computing requirements of the application. Their design consists of multiple “memory cores” (M-cores). Every M-core is a single crossbar which can perform computations using/inside local memory. Every M-core has multiple identical tiles that can be reconfigured to work as storage or digital/analog computing element. Thus, either an entire core or a tile can be assigned to a task, which allows multi-granularity reconfiguration to adapt to application needs.) [Mittal: page 86-87; Fig. 11] to participate in training and an operation mode of each of the switchable memories to participate in training (a ReRAM-based pipelined design for accelerating both training and testing of CNNs. They divide MCAs into two types: memory and morphable. The morphable MCAs can perform both computation and data-storage and memory MCAs can only store data) [Mittal: page 84] based on a structure and size of the AI neural network (They also proposed solutions for the cases when merging is required because of the need of storing positive and negative weights in two crossbars and when weight matrix needs to be stored in multiple crossbars due to the CNN size exceeding that of ReRAM crossbar. Their technique brings large reduction in area and energy with negligible impact on classification accuracy) [Mittal: page 90, Figs. 15-16], and then reconfigure the dataflow according to a result thereof (Imani et al. [63] implemented exact/inexact addition/multiplication operation using PIM capability of MCAs. They used a crossbar memory which is logically partitioned into memory and compute blocks, as shown in Figure 26a. These blocks connect with each other using reconfigurable interconnects that inherently support shift operations. Thus, data shifting can be done while copying it from one block to another without any additional delay. In addition, unlike bit-wise shifting, entire data can be shifted at once. Their adder is based on the 3:2 CSA (carry save adder) design, as shown in Figure 26c. It uses N 1-bit adders that produce two outputs each. The adders do not propagate any carry bit and, hence, can execute in parallel. Using their memory unit which supports shifts, they achieve CSA-like behavior. Finally, the two numbers are serially added. To add multiple numbers, they used a Wallace-tree-like design [77], which reduces delay by propagating the carry only at the last stage, although this design increases energy consumption and memory writes. The latency of their reduction adder is independent of the size of operands, e.g., N _ 32 multiplication takes same time irrespective of the value of N) [Mittal: page 98, Figs. 26]; (Li et al. notes that, in conventional training methods for MCA based NNs, first the parameters of memristors need to be found and then the MCA needs to be tuned to the target state. However, this process incurs latency/area/energy overhead and may also introduce errors. They proposed a mixed-signal framework for accelerating NN training. In “stochastic gradient descent algorithm” used for NN training, many multiplications are performed which are difficult to be realized in analog domain. To address this issue, they proposed approximating the error computations by ignoring values with small magnitude, such that the impact on the overall result is minimal. Further, they divide the weight update calculations into sign computation and numerical computation. Sign computation finds the direction of weight update and it can be realized through a zero-crossing detector and an analog comparator, as shown in Figure 16. The calculations between signs are realized in digital domain, which is beneficial also because the digital data can be cached more easily than the analog data. To avoid analog numerical computations, their technique automatically adjusts convergence rate and, if the convergence rate falls below a threshold, the training process is stopped. Further, convergence rate is multiplied with a random value between 0 and 1 to emulate fluctuation of values. To avoid caching the delta values and then importing them in the network, they use a copy crossbar which allows directly computing these values. Compared to a CPU implementation, their design achieves magnitude order higher performance and energy efficiency with only minor reduction in accuracy) [Mittal: page 90; Figs. 16, 26] to generate a dynamic core.
Mittal does not explicitly disclose the following claim limitations (Emphasis added).
generate a dynamic core.
However, in the same field of endeavor Ish further discloses the claim limitations and the deficient claim limitations, as follows:
generate a dynamic core (Aspects of the present disclosure are directed to dynamic
selection of cores for processing responses. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below
in conjunction with FIG. 1. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory
sub-system and can request data to be retrieved from the memory sub-system) [Ish: col. 1, line 46-56; Figs. 1-5]; (The core manager 150 can dynamically select, in response to receiving a read command, a core to process a read response that is different than the core used to process the read command. By allowing the core manager 150 to dynamically select cores for portions of the access operation,
the core manager 150 can reduce latency for performing portions of the read operation) [Ish: col. 6, line 1-10; Figs. 1-5].
It would have been obvious to one with an ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Mittal with Ish to program the system to implement of Ish’s method.
Therefore, the combination of Mittal with Ish will enable the system to reduce latency for performing portions of the read operation [Ish: col. 6, line 1-9].
Regarding claim 10, Mittal meets the claim limitations as set forth in claim 9. Mittal further meets the claim limitations as follow.
a first link switch ((FF subarrays) [Mittal: page 98, Fig. 25]; (DDR bus) [Mittal: Fig. 24]; (IO bus) [Mittal: Fig. 35]; (shared data bus) [Mittal: page 83; Figs. 7, 37]) configured to form a dataflow with at least one of other fixed memories and at least one of the switchable memories under control of the dynamic core generator (To switch the FF subarrays from memory to compute mode, data stored in them are moved to memory subarrays. Then, weights of the mapped NNs are written to the FF subarrays and the periphery is reconfigured. Opposite process happens on change from compute to memory mode) [Mittal: page 98, Fig. 25]; ; (local wordlines and device driver. Thus, by merely changing the read-circuit, their technique computes bitwise operations on multiple memory rows. The output can be written to the I/O bus or another memory row. Since their technique performs row-level operations only, the software need to allocate data in PIM-aware manner. Their technique can perform operations at intra-subarray, inter-subarray or inter-bank levels. Their technique achieves higher energy efficiency and performance compared to general-purpose processor and DRAM-based PIM technique) [Mittal: page 96; Fig. 29]); a global SRAM configured to store data necessary for the training (In addition, SRAM (static random access memory) is a volatile memory with high leakage energy and, since SRAM does not efficiently support a wide range of operations in
memory, SRAM-based designs such as TrueNorth use separate logic for performing computations) [Mittal: page 75]; and a buffer configured to buffer input/output data of the global SRAM (As shown in Figure 6, their design has three layers: two-layers of ReRAM crossbar and one-layer of CMOS circuitry. The first ReRAM-crossbar layer works as a buffer for storing the weights and is used for configuring the crossbar resistance values in the second layer. The tensor cores are 3D matrices and its 2D slices are stored on Layer 1. The second layer of MCA executes operations such as vector addition and MVM. This layer receives tensor cores from the first layer over through-silicon-via (TSV) for performing parallel MVM) [Mittal: page 75; Fig. 6].
Mittal does not explicitly disclose the following claim limitations (Emphasis added).
a dynamic core generator.
However, in the same field of endeavor Ish further discloses the claim limitations and the deficient claim limitations, as follows:
a dynamic core generator (The core manager 150 can dynamically select, in response to receiving a read command, a core to process a read response that is different than the core used to process the read command. By allowing the core manager 150 to dynamically select cores for portions of the access operation, the core manager 150 can reduce latency for performing portions of the read operation) [Ish: col. 6, line 1-10; Figs. 1-5].
It would have been obvious to one with an ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Mittal with Ish to program the system to implement of Ish’s method.
Therefore, the combination of Mittal with Ish will enable the system to reduce latency for performing portions of the read operation [Ish: col. 6, line 1-9].
Regarding claim 11, Mittal meets the claim limitations as set forth in claim 9. Mittal further meets the claim limitations as follow.
a second link switch ((FF subarrays) [Mittal: page 98, Fig. 25]; (DDR bus) [Mittal: Fig. 24]; (IO bus) [Mittal: Fig. 35]; (shared data bus) [Mittal: page 83; Figs. 7, 37]) configured to form a dataflow with at least one of other switchable memories and at least one of the fixed memories under control of the dynamic core generator ((To switch the FF subarrays from memory to compute mode, data stored in them are moved to memory subarrays. Then, weights of the mapped NNs are written to the FF subarrays and the periphery is reconfigured. Opposite process happens on change from compute to memory mode) [Mittal: page 98, Fig. 25]; ; (local wordlines and device driver. Thus, by merely changing the read-circuit, their technique computes bitwise operations on multiple memory rows. The output can be written to the I/O bus or another memory row. Since their technique performs row-level operations only, the software need to allocate data in PIM-aware manner. Their technique can perform operations at intra-subarray, inter-subarray or inter-bank levels. Their technique achieves higher energy efficiency and performance compared to general-purpose processor and DRAM-based PIM technique) [Mittal: page 96; Fig. 29]);
a switchable PIM array including a plurality of triple-mode memory cells each operating in any one operation mode among a computation mode, a memory mode, and a data conversion mode (Chi et al. proposed a PIM architecture for ReRAM-based main memory for accelerating NN computations. They divided a ReRAM bank into three types of subarrays: memory (Mem), buffer and full function (FF)) [Mittal: page 97-98; Fig. 25];a reconfigurable memory unit configured to operate as a computation control module for supporting a computation function or a buffer for data buffering depending on the operation mode of each of the memory cells (Mem subarrays only store data whereas FF subarrays can either store data or perform NN computations, as shown in Figure 25. Buffer subarrays buffer the data for FF subarrays without requiring involvement of CPU. FF subarrays benefit from high bandwidth of in-memory data
movement and ability to work in parallel to CPU) [Mittal: page 98; Fig. 25]; and a memory controller configured to determine the operation mode of each of the memory cells (FF subarrays benefit from high bandwidth of in-memory data movement and ability to work in parallel to CPU. They noted that an SA performs similar function as an ADC and same is also true for write drivers and DACs. Hence, with only small modifications, they reused write drivers and SAs to perform the function of DAC and ADC, respectively. This sharing of periphery between computation and memory lowers the area overhead) [Mittal: page 98; Fig. 25] under control of the dynamic core generator (FF subarrays benefit from high bandwidth of in-memory data movement and ability to work in parallel to CPU. They noted that an SA performs similar function as an ADC and same is also true for write drivers and DACs. Hence, with only small modifications, they reused write drivers and SAs to perform the function of DAC and ADC, respectively. This sharing of periphery between computation and memory lowers the area overhead) [Mittal: page 98; Fig. 25].
Mittal does not explicitly disclose the following claim limitations (Emphasis added).
a dynamic core generator.
However, in the same field of endeavor Ish further discloses the claim limitations and the deficient claim limitations, as follows:
a dynamic core generator (The core manager 150 can dynamically select, in response to receiving a read command, a core to process a read response that is different than the core used to process the read command. By allowing the core manager 150 to dynamically select cores for portions of the access operation, the core manager 150 can reduce latency for performing portions of the read operation) [Ish: col. 6, line 1-10; Figs. 1-5].
It would have been obvious to one with an ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Mittal with Ish to program the system to implement of Ish’s method.
Therefore, the combination of Mittal with Ish will enable the system to reduce latency for performing portions of the read operation [Ish: col. 6, line 1-9].
Allowable Subject Matter
18. Claims 2-8 and 12-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. This objection is given with a condition that all objections and rejections of related claims are addressed.
Reference Notice
Additional prior arts, included in the Notice of Reference Cited, made of record and not relied upon is considered pertinent to applicant's disclosure.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Philip Dang whose telephone number is (408) 918-7529. The examiner can normally be reached on Monday-Thursday between 8:30 am - 5:00 pm (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sath Perungavoor can be reached on 571-272-7455. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000./Philip P. Dang/Primary Examiner, Art Unit 2488
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