Prosecution Insights
Last updated: October 02, 2026
Application No. 18/644,372

MULTILAYER ELECTRONIC COMPONENT

Final Rejection §103
Filed
Apr 24, 2024
Priority
Aug 11, 2023 — RE 10-2023-0105577
Examiner
MCFADDEN, MICHAEL P
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electro-Mechanics Co., Ltd.
OA Round
2 (Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
729 granted / 844 resolved
+18.4% vs TC avg
Strong +20% interview lift
Without
With
+19.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
31 currently pending
Career history
851
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
61.1%
+21.1% vs TC avg
§102
30.1%
-9.9% vs TC avg
§112
4.6%
-35.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 844 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over ISHIDO et al (US 2023/0074009) in view of Isota et al (US 2017/0018358). Regarding claim 1, ISHIDO teaches a multilayer electronic component (Fig. 1-15), comprising: a body (Fig. 2) including a dielectric layer (Fig. 2, 2), a first internal electrode layer (Fig. ,2 5), and a second internal electrode layer (Fig. 2, 6) alternately disposed in a first direction (Fig. 2, left to right), with the dielectric layer interposed therebetween (Fig. 2); a first external electrode (Fig. 2, 8) disposed on one surface (Fig. 2, top surface) of two surfaces (Fig. 2, top and bottom) of the body opposing each other in a second direction (Fig. 2, up and down), perpendicular to the first direction (Fig. 2); and a second external electrode (Fig. 2, 10) disposed on the other surface of two surfaces of the body opposing each other in the second direction (Fig. 2), wherein the first internal electrode layer and the second internal electrode layer include first internal electrodes connected to the first external electrode (Fig. 2), and second internal electrodes connected to the second external electrode (Fig. 2), wherein the first and second internal electrodes are alternately disposed to be spaced apart from each other in a third direction (Fig. 6, up and down), perpendicular to the first (Fig. 6, left and right) and second directions (Fig. 6, in and out of the page), the first internal electrodes of the first internal electrode layer are alternately disposed with the second internal electrodes of the second internal electrode layer in the first direction (Fig. 6), and the second internal electrodes of the first internal electrode layer are alternately disposed with the first internal electrodes of the second internal electrode layer in the first direction (Fig. 6), wherein s ≥ td is satisfied, in which s is a distance in the third direction between one of the first internal electrodes and a second internal electrode, most adjacent to the one of the first internal electrodes in the third direction and td is a distance in the first direction between the one of the first internal electrodes and a second internal electrode, most adjacent to the one of the first internal electrodes in the first direction (Fig. 6, the distance between 5/6 in left to right is the same up and down so s = td, which teaches the claim limitation [0052]). However, ISHIDO fails to teach that the dielectric layer includes Ba and Ti. Isota teaches that the dielectric layer includes Ba and Ti ([0050]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Isota to the invention of ISHIDO, in order to increase the reliability of the capacitor with smaller dielectric layer (Isota [0037]). Regarding claim 2, ISHIDO, as modified by Isota, further teaches that 0.5 ≤ te/we ≤1.5 is satisfied, in which te is a maximum size in the first direction of the one of the first internal electrode and the second internal electrode which is most adjacent to the one of the first internal electrodes in the first direction and we is a maximum size in the third direction of the one of the first internal electrodes and the second internal electrode which is most adjacent to the one of the first internal electrodes in the third direction (Fig. 6, they would be the same as they form squares of equal size therefore te/we would be 1). Regarding claim 3, ISHIDO, as modified by Isota, further teaches that te ≤ td is satisfied, in which te is a maximum size in the first direction of the one of the first internal electrode and the second internal electrode which is most adjacent to the one of the first internal electrodes in the first direction (they would be the same 0.3-10 μm [0051-0052]). Regarding claim 4, ISHIDO fails to specifically teach the claim limitations. However, the examiner notes that the limitation of “wherein 50(te+td)≤ T is satisfied, in which te is a maximum size in the first direction of the one of the first internal electrode and the second internal electrode which is most adjacent to the one of the first internal electrodes in the first direction and T is a maximum size of the body in the first direction” is considered to be a result effective variable, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the invention to include the limitation of “wherein 50(te+td)≤ T is satisfied, in which te is a maximum size in the first direction of the one of the first internal electrode and the second internal electrode which is most adjacent to the one of the first internal electrodes in the first direction and T is a maximum size of the body in the first direction” as this limitation would be easily reached by one having ordinary skill in the art in order to construct the devices using understood variable specifications and designs in the art to best meet user needs based on known design possibilities. Regarding claim 5, ISHIDO fails to specifically teach the claim limitations. However, the examiner notes that the limitation of “wherein 50(s+we) ≤ W is satisfied, in which we is a maximum size in the third direction of the one of the first internal electrodes and the second internal electrode which is most adjacent to the one of the first internal electrodes in the third direction and W is a maximum size of the body in the third direction” is considered to be a result effective variable, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the invention to include the limitation of “wherein 50(s+we) ≤ W is satisfied, in which we is a maximum size in the third direction of the one of the first internal electrodes and the second internal electrode which is most adjacent to the one of the first internal electrodes in the third direction and W is a maximum size of the body in the third direction” as this limitation would be easily reached by one having ordinary skill in the art in order to construct the devices using understood variable specifications and designs in the art to best meet user needs based on known design possibilities. Regarding claim 6, ISHIDO fails to specifically teach the claim limitations. However, the examiner notes that the limitation of “wherein the first internal electrodes and the second internal electrodes are disposed in an amount of 25 or more layers in the first direction, respectively” is considered to be a result effective variable, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the invention to include the limitation of “wherein the first internal electrodes and the second internal electrodes are disposed in an amount of 25 or more layers in the first direction, respectively” as this limitation would be easily reached by one having ordinary skill in the art in order to construct the devices using understood variable specifications and designs in the art to best meet user needs based on known design possibilities. Regarding claim 7, ISHIDO fails to specifically teach the claim limitations. However, the examiner notes that the limitation of “wherein the first internal electrodes and the second internal electrodes are disposed in an amount of 25 or more layers in the third direction, respectively” is considered to be a result effective variable, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the invention to include the limitation of “wherein the first internal electrodes and the second internal electrodes are disposed in an amount of 25 or more layers in the third direction, respectively” as this limitation would be easily reached by one having ordinary skill in the art in order to construct the devices using understood variable specifications and designs in the art to best meet user needs based on known design possibilities. Regarding claim 8, ISHIDO fails to specifically teach the claim limitations. However, the examiner notes that the limitation of “wherein the number of first internal electrodes and second internal electrodes overlapping in the third direction is greater than the number of first internal electrodes and second internal electrodes overlapping in the first direction” is considered to be a result effective variable, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the invention to include the limitation of “wherein the number of first internal electrodes and second internal electrodes overlapping in the third direction is greater than the number of first internal electrodes and second internal electrodes overlapping in the first direction” as this limitation would be easily reached by one having ordinary skill in the art in order to construct the devices using understood variable specifications and designs in the art to best meet user needs based on known design possibilities. Regarding claim 9, ISHIDO, as modified by Isota, further teaches that the first internal electrodes and the second internal electrodes are disposed in a lattice shape in a cross-section of the multilayer electronic component in the first and third directions (Fig. 6). Regarding claim 10, ISHIDO, as modified by Isota, further teaches that the first internal electrodes and the second internal electrodes have a substantially square shape in the cross-section of the multilayer electronic component in the first and third directions (Fig. 8). Regarding claim 11, ISHIDO, as modified by Isota, further teaches that the first internal electrodes are spaced apart from the second external electrode, and the second internal electrodes are spaced apart from the first external electrode (Fig. 2). Regarding claim 12, ISHIDO, as modified by Isota, further teaches that the dielectric layer (Fig. 2, 7) is disposed in a space in which the first internal electrodes are spaced apart from the second external electrode and in a space in which the second internal electrodes are spaced apart from the first external electrode (Fig. 2). Regarding claim 13, ISHIDO, as modified by Isota, further teaches that the first internal electrode layer and the second internal electrode layer comprise a plurality of first internal electrodes and a plurality of second internal electrodes, and an internal electrode, most adjacent to the one of the first internal electrodes, is a second internal electrode (Fig. 2 and 6). Additional Relevant Prior Art: KOBAYASHI et al (US 2008/0129156) teaches relevant art in Fig. 1-10. Masuda et al (US 2009/0052110) teaches relevant art in Fig. 1-11. Masuda et al (US 2009/0154054) teaches relevant art in Fig. 1-3. LEE (US 2021/0082620) teaches relevant art in Fig. 1-19. LEE et al (US 2021/0183577) teaches relevant art in Fig. 1-10. Lee et al (US 2021/0183569) teaches relevant art in Fig. 1-13. Response to Arguments Applicant's arguments filed 06/30/2026 have been fully considered but they are not persuasive. In response to applicant's argument that the materials of Isota could not be incorporated into the invention of ISHIDO, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). The examiner notes that the use of a Ba or Ti based dielectric layer is well known in capacitors of all types and it would be an easy exchange to use one of these materials in a capacitor of various configurations that have dielectric materials separating conductive layer. The use of conventional materials/components to perform their known function is obvious. MPEP 2144.06. In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the teachings of Isota could be incorporated into the invention of ISHIDO, in order to increase the reliability of the capacitor with smaller dielectric layer (Isota [0037]). In response to applicant's argument that Isota is nonanalogous art, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case, both inventions are various builds of layered capacitor elements and it would be easy for one skilled in the art to swap parts and materials of one capacitor build into another. Applicant therefore does not provide any persuasive evidence that the limitations as claimed are not taught by the prior art. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P MCFADDEN whose telephone number is (571)270-5649. The examiner can normally be reached M-Thur 8am-9pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL P MCFADDEN/Primary Examiner, Art Unit 2847
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Prosecution Timeline

Apr 24, 2024
Application Filed
Mar 31, 2026
Non-Final Rejection mailed — §103
Jun 30, 2026
Response Filed
Aug 10, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+19.7%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 844 resolved cases by this examiner. Grant probability derived from career allowance rate.

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