Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: the “software component” in claim 9.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Objections
Claim 4 is objected to because of the following informalities: “therein” should be “wherein.” Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Antony (US 2015/0205542) and further in view of Franciosi (US 2019/0391843).
Regarding claim 1, Antony teaches: A method of transferring a guest virtual machine (VM) from a source node to a target node, the method comprising:
on the target node (¶ 18, “at step 204, virtualization management module 144 instantiates a new VM on the destination host corresponding to the source VM”), allocating a set of resources to be used by the guest VM (¶ 18, “the instantiated VM may be a placeholder virtual machine referred to as a "shadow" VM 304”), the set of resources including a designated system memory for the guest VM (¶ 18, “which acts as a reservation for computing resources (e.g., CPU, memory) on the destination host”);
following the re-mapping, begin copying system memory of the guest VM from the first physical memory region on the source node to the shared physical memory region on the transfer node (¶ 2, “copying source VM memory to the memory file using a storage interface of the source host while the source VM is in a powered-on state”);
stopping the guest VM on the source node (¶ 22, “At step 216, the source host stuns source VM 302 and releases the lock on memory file 310 associated with the source host”); and
resuming the guest VM on the target node (¶ 24, “At step 222, hypervisor 114 of destination host 102.sub.2 resumes operation of shadow VM 304 and begins copying data from memory file 310 into destination VM memory (e.g., vRAM 306) associated with destination VM using the storage interface 112 of the destination host”).
Antony does not teach; however, Franciosi discloses: on a transfer node, reserving a shared physical memory region that is to facilitate transfer of the guest VM from the source node to the target node (¶ 23, “Each of the first node 105, the second node 110, and the third node 115 may also be configured to communicate and share resources with each other via the network 165”), the shared physical memory region being part of a shared memory pool that is memory coherent and cache coherent with both the source node and the target node (¶ 25, “The ROM and RAM may both be part of the storage pool 170”);
while the guest VM is running on the source node, re-mapping VM system memory of the guest VM from a first physical memory region on the source node to the shared physical memory region on the transfer node (¶ 17, “the hypervisor at host machine A can indicate to the hypervisor of the host machine B that the shared host physical storage includes swapped out. The shared host physical storage can store mapping information that when accessed by the hypervisor at the host machine B provides the locations of the memory blocks that store the swapped out memory data from the memory of the host machine A”);
on the target node, mapping the designated system memory to the shared physical memory region on the transfer node (¶ 17, “The hypervisor at the host machine B can update its mapping tables to indicate the identities of the pages that have been swapped out and the locations in the shared host physical memory where the swapped pages reside”);
It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of on a transfer node, reserving a shared physical memory region that is to facilitate transfer of the guest VM from the source node to the target node, the shared physical memory region being part of a shared memory pool that is memory coherent and cache coherent with both the source node and the target node; while the guest VM is running on the source node, re-mapping VM system memory of the guest VM from a first physical memory region on the source node to the shared physical memory region on the transfer node; on the target node, mapping the designated system memory to the shared physical memory region on the transfer node, as taught by Franciosi, in the same way to the migrating a VM from a source node to a target node, as taught by Antony. Both inventions are in the field of migrating VMs, and combining them would have predictably resulted in avoiding “offline virtual machines [which] result in downtime to a user, which may be unacceptable,” as indicated by Franciosi (¶ 14).
Regarding claim 2, Franciosi teaches: The method of claim 1, wherein mapping the designated system memory to the shared physical memory region is performed before stopping the guest VM (¶ 54, “by sharing the shared host physical storage 260 and by maintaining metadata 264 on the shared host physical storage 260, the second hypervisor 222 can readily access the swapped out memory data associated with the migrated first virtual machine 214. By avoiding the swapping in of the swapped out memory data, the delay time associated with the migration of the first virtual machine 214 is reduced”).
Regarding claim 3, Antony teaches: The method of claim 2, wherein stopping the guest VM on the source node and resuming of the guest VM on the target node are performed substantially concurrent to one another (¶ 22, “hypervisor 114 may momentarily quiesce source VM 302 during the switchover to the destination host to prevent further changes to the memory state of source VM 302”).
Claims 17-19 recite commensurate subject matter as claims 1-3. Therefore, they are rejected for the same reasons.
Claim(s) 4, 9-12, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Antony and Franciosi, as applied above, and further in view of Alden (US 2024/0176739).
Regarding claim 4, Antony and Franciosi do not teach; however, Alden discloses: the transfer node includes a multi-port switch controller coupled to the target node and the source node (¶ 3, “one or more cache coherent switches comprising two or more host ports and one or more downstream device ports” and “a first compute node comprising a first processor and a first cache, the first compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes; and a second compute node comprising a second processor and a second cache, the second compute node in electrical communication with the one or more cache coherent switches and the one or more shared memory complexes”).
It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of the transfer node includes a multi-port switch controller coupled to the target node and the source node, as taught by Alden, in the same way to the transfer node, as taught by Antony and Franciosi. Both inventions are in the field of shared memory configurations, and combining them would have predictably resulted in a method to “make use of resource redundancy and failover mechanisms,” as indicated by Alden (¶ 2).
Claims 9-12 and 20 recite commensurate subject matter as claims 1-4. Therefore, they are rejected for the same reason.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Antony and Franciosi, as applied above, and further in view of Das Sharma (US 2018/0004558).
Regarding claim 5, Antony and Franciosi do not teach; however, Das Sharma discloses: the transfer node, the target node, and the source node all reside in a same rack (¶ 16, “One or more trays may be used in a rack scale system;” ¶ 17, “each tray 110, 150 may include multiple nodes 120 connected to pooled memory 102 via a shared memory controller (SMC) 104, 154;” and “the VM migration can be within the same tray 110”).
It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of the transfer node, the target node, and the source node all reside in a same rack, as taught by Das Sharma, in the same way to the transfer node, as taught by Antony and Franciosi. Both inventions are in the field of shared memory configurations, and combining them would have predictably resulted in a method to “make use of resource redundancy and failover mechanisms,” as indicated by Das Sharma (¶ 2).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Antony and Franciosi, as applied above, and further in view of Gopalan (US 2014/0196037).
Regarding claim 6, Antony and Franciosi do not teach; however, Gopalan discloses: the source node is in a different rack than the target node (¶ 37, “we first describe how GMGD operates when VMs are live migrated from one rack of machines to another rack”) and wherein mapping the designated system memory to the shared physical memory region is performed after stopping the guest VM on the source node and subsequent to completion of the copying of the system memory from the first physical memory region on the source node to the shared physical memory region on the transfer node (¶ 73, “The source QEMU/KVM process is prevented from starting the VM downtime and keep it in the live pre-copy iteration mode until all of its pages have been retrieved at the target and copied into memory. Once all remote pages are in place, the source is instructed by the target to initiate the downtime. This allows VMs to minimize their downtime, as only the remaining dirty pages at the source are transferred during the downtime”).
It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of the source node is in a different rack than the target node and wherein mapping the designated system memory to the shared physical memory region is performed after stopping the guest VM on the source node and subsequent to completion of the copying of the system memory from the first physical memory region on the source node to the shared physical memory region on the transfer node, as taught by Gopalan, in the same way to the transfer node, as taught by Antony and Franciosi. Both inventions are in the field of shared memory configurations, and combining them would have predictably resulted in a method that “optimizes the live migration of a single VM over wide-area network through a variant of stop-and-copy approach which reduces the number of memory copying iterations,” as indicated by Gopalan (¶ 5).
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Antony and Franciosi, as applied above, and further in view of Hyatt (US 2024/0256441).
Regarding claim 7, Antony and Franciosi do not teach; however, Hyatt teaches: the designated system memory on the target node is defined by a set of logical addresses (¶ ¶ 26, “hypervisor allocates memory to virtual machines (VMs), and assigns each VM its own address space (at the hypervisor's level)”) and wherein allocating the set of resources on the target node further comprises creating a memory map on the target node that maps the set of logical addresses to a local memory region on the target node (¶ 38, “the resource composer configures the IOMMU or MMU on the second host, adding entries that map remote physical pages to local virtual pages, which provides the second host with seamless access to memory resources located on the first host”), and wherein mapping the designated system memory to the shared physical memory region further comprises re-mapping the set of logical addresses from the local memory region on the target node to the shared physical memory region (¶ 36, “the resource composer proceeds to map the corresponding page frames, which point to DRAM on the first host, to the address space of a second process P2 operating in PCE2 on the second host”).
It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of the designated system memory on the target node is defined by a set of logical addresses and wherein allocating the set of resources on the target node further comprises creating a memory map on the target node that maps the set of logical addresses to a local memory region on the target node, and wherein mapping the designated system memory to the shared physical memory region further comprises re-mapping the set of logical addresses from the local memory region on the target node to the shared physical memory region, as taught by Hyatt, in the same way to the transfer node, as taught by Antony and Franciosi. Both inventions are in the field of VM memory mapping, and combining them would have predictably resulted in “establishing a high-speed communication channel that facilitates efficient memory management and resource allocation,” as indicated by Hyatt (¶ 4).
Regarding claim 8, Franciosi teaches: The method of claim 7, further comprising: subsequent to completion of the copying of the system memory of the guest VM from the first physical memory region on the source node to the shared physical memory region on the transfer node, begin copying the system memory from the shared physical memory region on the transfer node to the local memory region on the target node (claim 10, “the second host machine further copies at least a portion of the second portion from the shared storage to the second memory in response to the page fault”); and re-mapping the set of logical addresses of the designated system memory from the shared physical memory region to the local memory region on the target node (claim 13, “updating a mapping table on the second host machine with the location of the second memory data in the shared storage for access during a page fault”).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Antony, Franciosi, and Alder, as applied above, and further in view of Das Sharma.
Claim 13 recites commensurate subject matter as claim 5. Therefore, it is rejected for the same reason.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Antony, Franciosi, and Alder, as applied above, and further in view of Gopalan.
Claim 14 recites commensurate subject matter as claim 6. Therefore, it is rejected for the same reason.
Claim(s) 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Antony, Franciosi, and Alder, as applied above, and further in view of Hyatt.
Claims 15 and 16 recites commensurate subject matter as claims 7 and 8. Therefore, they are rejected for the same reason.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB D DASCOMB whose telephone number is (571)272-9993. The examiner can normally be reached M-F 9:00-5:00.
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/JACOB D DASCOMB/ Primary Examiner, Art Unit 2198
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